XADC Overview
The XADC includes a dual 12-bit, 1 Mega sample per second (MSPS) ADC and on-chip sensors. The ADCs and sensors are fully tested and specified (see the respective 7 series FPGAs data sheet ). The ADCs provide a general-purpose, high-precision analog interface for a range of applications. Figure 1-1 shows a block diagram of the XADC. The dual ADCs support a range of operating modes, for example, externally triggered and simultaneous sampling on both ADCs (see Chapter 4, XADC Operating Modes ) and various analog input signal types, for example, unipolar and differential (see Chapter 2, Analog-to-Digital Converter ). The ADCs can access up to 17 external analog input channels.
Notes relevant to Figure 1-1 :
1. Zynq-7000 SoC devices only.
The XADC also includes several on-chip sensors that support measurement of the on-chip power supply voltages and die temperature. The ADC conversion data is stored in dedicated registers called status registers. These registers are accessible through the FPGA interconnect using a 16-bit synchronous read and write port called the dynamic reconfiguration port (DRP). ADC conversion data is also accessible through the JTAG TAP, either before (pre-configuration) or after configuration. For JTAG TAP, users are not required to instantiate the XADC because it is a dedicated interface that uses the existing FPGA JTAG infrastructure. As discussed later, if the XADC is not instantiated in a design, the device operates in a predefined mode (called default mode ) that monitors on-chip temperature and supply voltages.
XADC operation is user defined by writing to the control registers using either the DRP or JTAG interface. It is also possible to initialize these register contents when the XADC is instantiated in a design using the block attributes.
Differences between Virtex-5 and Virtex-6 System Monitors
For Virtex-5 and Virtex-6 FPGA System Monitor users, the XADC functionality is fully backward compatible with legacy System Monitor designs. The XADC functionality and interface are familiar to those who have previously designed with the System Monitor. System Monitor designs are automatically retargeted to the XADC site by the software tools.
However, the XADC block in 7 series FPGAs contains a large number of new features and enhancements detailed in subsequent chapters. The new functionality is enabled by initializing previously undefined status registers and bit locations. Old System Monitor designs that did not initialize these new registers or bit locations behave exactly the same way as before.