XADC Pinout Requirements

Dedicated Package Pins

All XADC dedicated pins are located in bank 0 and thus have the _0 suffix in the package file names. Figure 1-2 shows the basic pinout requirements for the XADC. There are two recommended configurations. On the left, the XADC is powered from V _CCAUX (1.8V) and uses an external 1.25V reference source. The external reference delivers the best performance in terms of accuracy and thermal drift. A ferrite bead is used to isolate the ground reference for the analog circuits and system ground. An additional low-pass filter for VCCAUX supply will similarly improve the ADC performance. See Chapter 6, Application Guidelines for more information. Shared or common ground impedance is the most common way to introduce unwanted noise into analog circuits.

Figure 1-2: XADC Pinout Requirements
X-Ref Target - Figure 1-2

It is also possible to use an on-chip reference for the ADCs. To enable the on-chip reference source, the V _REFP pin must be connected to ground as shown on the right of Figure 1-2 . Where only basic on-chip thermal and supply monitoring is required, using the on-chip reference provides good performance. Users should consult the respective data sheet to see the accuracy specifications when using the external and on-chip reference sources. Table 1-1 lists the pins associated with the XADC and the recommended connectivity.

Note: It is also important to place the 100 nF decoupling capacitors as close as possible to the package balls to minimize inductance between the decoupling and package balls.

Table 1-1: XADC Package Pins
Package Pin	Type	Description
V _{CCADC_0}	Power supply	This is the analog supply pin for the ADCs and other analog circuits in the XADC. It can be tied to the 1.8V V _CCAUX supply; however, in a mixed-signal system, the supply should be connected to a separate 1.8V analog, if available. See Analog Power Supply and Ground (V _CCADC and GNDADC), page 65 for more information. This pin should never be tied to GND. The pin should be tied to V _CCAUX even if the XADC is not being used.
GNDADC_0	Power supply	This is the ground reference pin for the ADCs and other analog circuits in the XADC. It can be tied to the system ground through an isolating ferrite bead as shown in Figure 1-2 . In a mixed-signal system this pin should be tied to an analog ground plane if available, in which case the ferrite bean is not required. See Analog Power Supply and Ground (V _CCADC and GNDADC), page 65 for more information. This pin should always be tied to GND even if the XADC is not being used.
V _{REFP_0}	Reference voltage input	This pin can be tied to an external 1.25V accurate reference IC (±0.2% or ±9 LSBs at 12 bits) for best performance of the ADCs. It should be treated as an analog signal that together with the V _REFN signal provides a differential 1.25V voltage. By connecting this pin to GNDADC (see Figure 1-2 ), an on-chip reference source (±1% or ±41 LSBs at 12 bits) is activated. This pin should always be connected to GNDADC if an external reference is not supplied. See Reference Inputs (V _REFP and V _REFN ), page 65 for more information.
V _{REFN_0}	Reference voltage input	This pin should be tied to the GND pin of an external 1.25V accurate reference IC (±0.2%) for best performance of the ADCs. It should be treated as an analog signal that together with the V _REFP signal provides a differential 1.25V voltage. This pin should always be connected to GND even if an external reference is not supplied. See Reference Inputs (V _REFP and V _REFN ), page 65 for more information.
V _{P_0}	Dedicated analog input	This is the positive input terminal of the dedicated differential analog input channel (V _P /V _N ). The analog input channels are very flexible and support multiple analog input signal types. For more information, see Analog Inputs, page 21 . This pin should be connected to GND if not used.
V _{N_0}	Dedicated analog input	This is the negative input terminal of the dedicated differential analog input channel (V _P /V _N ). The analog input channels are very flexible and support multiple analog input signal types. For more information, see Analog Inputs, page 21 . This pin should be connected to GND if not used.
_AD0P_ to _AD15P_ ⁽¹⁾ ⁽²⁾	Auxiliary analog inputs/digital I/O	These are multi-function pins that can support analog inputs or can be used as regular digital I/O (see Figure 1-1 ). These pins support up to 16 positive input terminals of the differential auxiliary analog input channels (V _AUXP /V _AUXN ). The analog input channels are very flexible and support multiple analog input signal types. For more information, see Analog Inputs, page 21 . When not being used as analog inputs, these pins can be treated like any other digital I/O.
_AD0N_ to _AD15N_ ⁽¹⁾ ⁽²⁾	Auxiliary analog inputs/digital I/O	These are multi-function pins that can support analog inputs or can be used as regular digital I/O (see Figure 1-1 ). These pins support up to 16 negative input terminals of the differential auxiliary analog input channels (V _AUXP /V _AUXN ). The analog input channels are very flexible and support multiple analog input signal types. For more information, see Analog Inputs, page 21 . When not being used as analog inputs, these pins can be treated like any other digital I/O.
Notes: 1. FPGA I/Os that are analog input-enabled contain the _ADxP_ and _ADxN_ designation in the package file name, for example, IO_L1P_T0_ AD0P _35 is the input pin for analog auxiliary channel VAUXP[0]. IO_L1N_T0_ AD0N _35 is the input pin for analog auxiliary channel VAUXN[0]. For more information, see UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide [Ref 2] . 2. Auxiliary channels 6, 7, 13, 14, and 15 are not supported in Kintex-7 devices. Some auxiliary analog channels might also not be supported in certain Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC device package options. You should consult the package file for the device.

Note: Chapter 6, Application Guidelines , should be consulted before commencing any PC board layout. Board layout and external component choices can greatly impact the performance of the ADCs.

External Analog Inputs

Apart from a single dedicated analog input pair (V _P /V _N ), the external analog inputs use dual-purpose I/O. These FPGA digital I/Os are individually nominated as analog inputs when the XADC is instantiated in a design. This document refers to these analog inputs as auxiliary analog inputs. A maximum of 16 auxiliary analog inputs are available. The auxiliary analog inputs are enabled by connecting the analog inputs on the XADC primitive to the top level of the design. When enabled as analog inputs, these package balls are unavailable as digital I/Os. It is also possible to enable the auxiliary analog inputs preconfiguration (for example, for PCB diagnostics) through the JTAG TAP (see JTAG DRP Commands for more information.)

All analog input channels are differential and require two package balls. Typically, the auxiliary analog inputs are allocated evenly over banks 15 and 35. However, users should consult the pinout information in UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide [Ref 2] for a particular device and package combination. Analog-capable I/O have the ADxP or ADxN suffix on the I/O name in the package files. For example, auxiliary analog input channel 8 has associated package ball names ending with AD8P and AD8N. See UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide [Ref 2] for more information. The auxiliary analog inputs have a fixed package ball assignment and cannot be moved.

Auxiliary analog inputs are supported differently in Vivado® tools when compared to ISE tools. The auxiliary analog inputs do not require any user-specified constraints or pin locations in ISE tools. ISE external auxiliary inputs do not need an I/O standard setting to be added to your constraints file (UCF) or in the PlanAhead ™ design tool. In Vivado design tools, the auxiliary analog inputs must be assigned to the associated pin location.

Auxiliary analog inputs must be connected to the top level of the design.

Note: Auxiliary channels 6, 7, 13, 14, and 15 are not supported on Kintex-7 devices. Some auxiliary analog channels might also not be supported in certain Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC device package options. Users should consult the package file for the device.