Zynq-7000 SoC Processing System (PS) to XADC Dedicated Interface
The DRP JTAG interface described in DRP JTAG Interface, page 40 is also used to provide a dedicated interface between the processor subsystem and the XADC block located in the programmable logic region of the Zynq-7000 SoC. This dedicated interface does not require the programmable logic to be configured. All the XADC functionality can be accessed by writing to and reading from the XADC status and configuration registers. For more details on how to enable this interface and programming models, see UG585, Zynq-7000 All Programmable SoC Technical Reference Manual [Ref 4] .
Note: When this interface is enabled, external JTAG access to the XADC as described in DRP JTAG Interface, page 40 is no longer supported.
Figure 3-8 illustrates a simplified block diagram of the interface between the processor subsystem and the XADC block. To simplify the interface and also reduce the overhead on the processor, two 32-bit FIFOs have been implemented. Up to 15 32-bit DRP JTAG command words (see Table 3-13 ) can be loaded into the command FIFO. The control logic in the interface manages the parallel to serial conversion and writing the commands to the DRP JTAG interface. Serial data shifted out on TDO on the DRP JTAG interface is converted to a 32-bit parallel word and written to the DRP JTAG Read Data FIFO which is also 15 words deep. XADC read data is accessed by the processor by reading from this FIFO. The same timing and protocol as detailed in DRP JTAG Interface, page 40 , applies to this interface.
The XADC alarm signals OT and ALM[6:0] are also connected to this dedicated interface. These signals generate interrupts when the XADC automatic alarms go active. For more information, see Automatic Alarms, page 56 .