3-State Control

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
Release Date
1.14 English

The transmitter side of a RXTX_BITSLICE and thereby a TX_BITSLICE provides two possibilities to 3-state an output buffer in an IOB. The two ways to 3-state can be seen as per channel block 3-state and as a nibble based per bit 3-state in a serial stream 3-state.

Each RXTX_BITSLICE and thus each TX_BITSLICE has a T input. The input is a combinatorial feed through of the 3-state signal generated in the FPGA logic to the T input of an output buffer in the IOB. This is called block 3-state because the serial output at the output buffer is 3-stated for an amount of bit periods. When 3-state of serial outputs must occur on a specified bit or bits in the serial stream, a combination of the BITSLICE_CONTROL.TBYTE_IN[3:0] inputs with a TX_BITSLICE_TRI must be used. The output of the TX_BITSLICE_TRI is routed to and through the TX_BITSLICEs to the 3-state input of an output buffer.

The output of the TX_BITSLICE_TRI is a serial stream that can be connected to all TX_BITSLICEs in a nibble and in this way, to all 3-state output buffer inputs. Four bits written at the TBYTE_IN inputs of the BITSLICE_CONTROL determine the 3-state occurrence in a serial stream. See the 3-state explanation in TX_BITSLICE_TRI.