BISC Calibration Steps

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The BISC controller tunes the delay line in TIME mode of each connected bit slice separately. BISC starts with the bit slice in position 0 and works its way up the nibble. When done, the DLY_RDY status signal is pulled High.

When the SELF_CALIBRATE attribute is set or when the RIU CALIB_CTRL register CALIBRATE (bit_0) and/or CALIBRATE_EN (bit_3:10) are used, the BISC controller runs three basic steps when tuning the delay lines. All steps are explained in the subsequent sections and shown in This Figure.

Figure 2-73:      Delay Calibration by BISC

 

X-Ref Target - Figure 2-73

X16790-delay-calibration-by-bisc.jpg

When bit slice delay lines are used in COUNT mode, the BISC calibration cycle runs but ignores the calibration and VT compensation for the primitives in COUNT mode delay lines.

In TIME mode, the auto-VT tracking can be turned on or off using attributes (I, O, Q DLY_VT_TRACK) or using bits in the RIU CALIB_CNTRL register.