The data and clock/strobe base handling block are the RXTX_BITSLICE (RX_BITSLICE and TX_BITSLICE primitives are derived from this component), which are used per pin or pin pair. The six or seven bit slices within a nibble are all controlled by one BITSLICE_CONTROL block, as shown in This Figure. Seven bit slices make an upper nibble and six bit slices assemble a lower nibble.
Base functions of the BITSLICE_CONTROL primitive (This Figure) are to perform built-in self-calibration (BISC), generate clocks for the receiver and transmitter functions in the RXTX_BITSLICEs, control specialized functions such as RX_ and/or TX_GATING, and control a set of registers (RIUs) used by the previous summed functions. Each of these functions is discussed separately later in this document. Pins and attributes allow a fair amount of control of the BITSLICE_CONTROL component, however, full control is obtained through a register interface unit (RIU). The RIU makes the BITSLICE_CONTROL act as a processor peripheral and gives access to a set of sixty-four 16-bit registers providing access to all the required delay and control values for the nibble group being programmed.
Two nibbles can be combined into a byte. A byte contains two BITSLICE_CONTROL components, each having an RIU interface. Both RIU interfaces can be combined using an RIU_OR component. When the RIU interfaces of both BITSLICE_CONTROLs are combined using a RIU_OR primitive it looks like a single RIU interface to the interconnect logic.
These aspects of the BITSLICE_CONTROL primitive are discussed later in this chapter: