BITSLICE_CONTROL Attributes

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: BITSLICE_CONTROL Attributes lists BITSLICE_CONTROL attributes. Most of these attributes have an equivalent register bit or bits in the RIU.

Table 2-31:      BITSLICE_CONTROL Attributes

Attribute

Value

Default

Type

Description

EN_OTHER_PCLK

TRUE

FALSE

FALSE

String

Enable inter-nibble clocking.

When set to TRUE, the PCLK is sourced from the other BITSLICE_CONTROL in the byte.

If this is turned on for one BITSLICE_CONTROL, it cannot be turned on for the other BITSLICE_CONTROL in the same byte.

EN_OTHER_NCLK

TRUE

FALSE

FALSE

String

Enable inter-nibble clocking. When set to TRUE, the NCLK is sourced from the other BITSLICE_CONTROL in the byte.

If this is turned on for one BITSLICE_CONTROL, it cannot be turned on for the other BITSLICE_CONTROL in the same byte.

SERIAL_MODE

TRUE

FALSE

FALSE

String

When set to TRUE, the master input clock, PLL_CLK or REFCLK, and the divided versions are used as the sample clock for the deserializer of a bit slice.

When set to FALSE, the clock or strobe applied to a BITSLICE_0 is used as sample clock.

When only data or data with embedded clock are applied to bit slices, use the SERIAL_MODE. The main function of the bit slices is to sample an incoming data stream with a clock generated from an internal, unrelated to the data source, such as a PLL.

RX_CLK_PHASE_P

SHIFT_0 SHIFT_90

SHIFT_0

String

Shifts the P-edge of the read clock by 0 degrees or 90 degrees relative to the captured data.

Data is sampled by a clock in the middle of a bit period. When clock and data arrive at the pin phase-aligned, use a shift by 90 degrees, or else leave this attribute at the default value.

When using SHIFT_90, DELAY_VALUE (RX_BITSLICE) or RX_DELAY_VALUE (RXTX_BITSLICE) must be 0.

RX_CLK_PHASE_N

SHIFT_0 SHIFT_90

SHIFT_0

String

Shifts the N-edge of the read clock by 0 degrees or 90 degrees relative to the captured data.

Data is sampled by a clock in the middle of a bit period. When clock and data arrive at the pin phase-aligned, use a shift by 90 degrees, or else leave this attribute at the default value.

When using SHIFT_90, DELAY_VALUE (RX_BITSLICE) or RX_DELAY_VALUE (RXTX_BITSLICE) must be 0.

INV_RXCLK

TRUE

FALSE

FALSE

String

Invert the read or sample CLK applied to BITSLICE_0.

TX_GATING

DISABLE

ENABLE

DISABLE

String

Write clock gating. For aligned transmitted data, TX_GATING must set to ENABLE and control the TBYTE_IN from interconnect logic.

Read Native Mode Bring-up and Reset for more information.

Note:   TX_GATING = ENABLE does not stop the clock for BITSLICE_1 and BITSLICE_6.

When TX_GATING = ENABLE, TBYTE_IN[3:0] is used to stop the clock for transmit interfaces.

RX_GATING

DISABLE ENABLE

DISABLE

String

Enables read strobe/clock gating.

The value of this attribute and the mechanism behind it is to gate in the strobe/clock during its preamble. Gate off the strobe/clock immediately following each of its falling edges and enable it afterward.

The gating circuit used by the attribute is only available in BITSLICE_0 of a nibble because strobe/clock can only be input from the BITSLICE_0 location in a nibble.

When set to TRUE, the gate is controlled by the BITSLICE_CONTROL.PHY_RDEN input.

READ_IDLE_COUNT[5:0]

0 to 63

0

Decimal

Number of clocks after PHY_RDEN deassertion and before turning off ODT termination.

MIG USE ONLY.

DIV_MODE

DIV2

DIV4

DIV2

String

Determines how the master clock is divided.

When 8-bit mode is used (1:8 serial input), set to DIV4.

When 4-bit mode is used, set to DIV2. The FIFO_WRCLK_OUT clock reflects the action of this attribute.

REFCLK_SRC

PLLCLK, REFCLK

PLLCLK

String

When the master clock is the PLL_CLK, this attribute should be set to PLLCLK.

When the master clock is the REFCLK input (RX_BITSLICE only), this attribute must be set to REFCLK.

ROUNDING_FACTOR

1, 2, 4, 8, 16, 32, 64, 128

16

Decimal

Rounding factor for BISC.

MIG USE ONLY.

CTRL_CLK

EXTERNAL

EXTERNAL

String

Defines the clock source for the RIU interface. Always use the default value, EXTERNAL.

EN_CLK_TO_EXT_NORTH

ENABLE DISABLE

DISABLE

String

Enable inter-byte strobe/clock forwarding to another upper byte BITSLICE_CONTROL.

EN_CLK_TO_EXT_SOUTH

ENABLE DISABLE

DISABLE

String

Enable inter-byte strobe/clock forwarding to another lower byte BITSLICE_CONTROL

EN_DYN_ODLY_MODE

TRUE

FALSE

FALSE

String

MIG USE ONLY.

SELF_CALIBRATE

ENABLE DISABLE

ENABLE

String

Built-in self-calibration (BISC) enable.

When set to ENABLE, BISC runs initial calibration after release of reset.

When set to DISABLE, calibration is not run after release of reset.

IDLY_VT_TRACK

TRUE

FALSE

TRUE

String

Enables voltage and temperature tracking for all input delays in a nibble.

ODLY_VT_TRACK

TRUE

FALSE

TRUE

String

Enables voltage and temperature tracking for all output delays in a nibble.

QDLY_VT_TRACK

TRUE

FALSE

TRUE

String

Enables voltage and temperature tracking for the quarter delays in the BITSLICE_CONTROL. Quarter delays are used to shift the clock relative to the incoming data.

RXGATE_EXTEND

TRUE

FALSE

FALSE

String

MIG USE ONLY.

SIM_DEVICE

Possible Values: ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2

ULTRASCALE

String

Sets the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)