BITSLICE_CONTROL Ports

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: BITSLICE_CONTROL Ports lists the BITSLICE_CONTROL ports.

Table 2-30:      BITSLICE_CONTROL Ports

Port

I/O

Synchronous Clock Domain

Description

PLL_CLK

Input

Asynchronous

Master clock input for the BITSLICE_CONTROL. Set REFCLK_SRC attribute = PLL_CLK.

This clock is used by the BISC controller. When SERIAL_MODE = TRUE, it is also used for data and strobe/clock sample clock.

This clock must come from one of the two PLLs in the I/O bank where the BITSLICE_CONTROL port carrying these pins is located.

The PLL connects to the PLL_CLK pin over dedicated, very low jitter routing.

Use this PLL_CLK clock input, or the REFCLK clock input, but not both. When the PLL_CLK is used, tie the REFCLK Low.

REFCLK

Input

Asynchronous

Master clock input for the BITSLICE_CONTROL. Set REFCLK_SRC attribute = REFCLK. REFCLK is only supported for RX_BITSLICE.

This clock is used by the BISC controller. When SERIAL_MODE = TRUE, it is also used for data and strobe/clock sample clock.

This clock can be generated by a MMCM in the internal logic.

Connections to this clock input use clock buffers and route over normal clock routing in the FPGA.

Use this REFCLK clock input, or the PLL_CLK clock input, but not both. When the REFCLK is used, tie the PLL_CLK Low.

It is recommended to use the PLL_CLK input of the BITSLICE_CONTROL. The master clock has very low jitter because it is generated by a PLL.

RST

Input

Asynchronous

Asynchronous asserted global reset.

This reset is best synchronously released, following a dedicated reset sequence.

Read the Native Mode Bring-up and Reset section for more information.

Note:   The reset for all used IDELAYCTRLs/BITSLICE_CONTROLs within a bank must be released at the same time due to the cascaded DLY_RDY connections between the BITSLICE_CONTROLs. Failure to do so might result in DLY_RDY for one of the IDELAYCTRLs/BITSLICE_CONTROLs not asserting.

EN_VTC

Input

RIU_CLK

Enable voltage and temperature control and tracking.

Assertion of EN_VTC maintains the delay of the delay lines that are in TIME mode over the V and T changes.

After DLY_RDY goes High and initial BISC completion, the EN_VTC signal must be pulled High.

There are also EN_VTC pins on the bit slices. For BISC to compensate the delays over VT, the BITSLICE.EN_VTC must be held High.

DLY_RDY

Output

Asynchronous

Status bit indicating when BISC finishes initial fixed delay line calibration.

This pin is also represented by a RIU register bit.

VTC_RDY

Output

Asynchronous

Status signal indicating when BISC finishes baseline VT calibration and tracking.

From now on, BISC continuously compensates the delay lines for voltage and temperature.

After asserted, this signal stays High until a hardware reset of the BITSLICE_CONTROL or its EN_VTC is toggled Low.

This pin is also represented by a RIU register bit. In Component mode, the IDELAYCTRL.RDY signal is the equivalent of this pin.

RIU_CLK

Input

Asynchronous

Clock for the RIU interface peripheral.

This clock is independent from all other BITSLICE_CONTROL clocks.

This clock can be generated by an MMCM or PLL.

RIU_ADDR[5:0]

Input

RIU_CLK

The address input bus provides a register address for the register interface.

The address value on this bus specifies the configuration and status bits that are written or read with the next RIU_CLK cycle. When not used, all bits must be assigned zeros.

RIU_WR_DATA [15:0]

Input

RIU_CLK

This input bus provides data. The value of this bus is written to the register address selected by RIU_ADDR of the register interface. The data is presented in the cycle that RIU_WR_EN and RIU_NIBBLE_SEL are active. The data is captured in a shadow register and written at a later time.

RIU_VALID indicates when the RIU port is ready to accept another write. When not used, all bits must be set to zero.

RIU_RD_DATA [15:0]

Output

RIU_CLK

This output bus provides RIU data to the internal logic. The value of this bus is a representation of the register bits addressed by RIU_ADDR. The data is presented in the next cycle when RIU_WR_EN is Low and RIU_NIBBLE_SEL is High, sampled by RIU. For a complete listing of RIU_RD_DATA information, see Register Definitions and Addresses.

RIU_VALID

Output

RIU_CLK

This signal indicates the status when RIU accesses are made from interconnect logic while the internal BISC state machines are also accessing the RIU registers. During a collision (i.e., an RIU write access from interconnect occurs during a BISC write access), the RIU_VALID signal deasserts. The internal logic write access still succeeds but not until RIU_VALID is asserted. No further action is required from interconnect logic except that no further RIU accesses are possible until RIU_VALID is deasserted High. In addition to collisions, the RIU_VALID asserts when writing to the RL_DLY_RNK[0, 1, 2, 3] registers. These registers are unique because it takes more than two cycles for an RIU write to update them. Therefore, back-to-back accesses to these registers are impossible.

RIU_WR_EN

Input

RIU_CLK

Signal must be High to write a register in an RIU interface.

RIU_NIBBLE_SEL

Input

RIU_CLK

Signal is used to select a nibble RIU in a byte. Must be High to perform write or read.

PHY_RDCS0 [3:0]

PHY_RDCS1 [3:0]

Input

PLL_CLK

Memory interface generator (MIG) use only: Rank select.

PHY_WRCS0 [3:0]

PHY_WRCS1 [3:0]

Output

PLL_CLK

TBYTE_IN[3:0]

Input

PLL_CLK

Nibble/byte group 3-state input.

When this input is used, a TX_BITSLICE_TRI primitive must be instantiated and connected to the TX_BIT_CTRL_OUT(IN)_TRI[39:0] buses, and TX_GATING must be set to ENABLE.

The nibble provided here is passed through the BITSLICE_CONTROL to the TX_BITSLICE_TRI primitive where the bits are serialized and delayed when the output delay line is used. The serial output of the TX_BITSLICE_TRI is passed to the single bit TBYTE_IN input of all used TX_BITSLICEs.

Read more about this input in the TX_BITSLICE and TX_BITSLICE_TRI sections.

PHY_RDEN[3:0]

Input

PLL_CLK

Read enable.

Must be tied to 1111 when the RX_GATING attribute is not used.

DYN_DCI[6:0]

Output

Asynchronous

MIG USE ONLY: Direct IOB DCI control.

The following ports are dedicated clock inputs and outputs between two BITSLICE_CONTROL components of the same byte or between bytes. The clock routing possibilities are enabled through the setting of attributes. For a discussion about the clocking possibilities between nibbles (inter-nibble) or between bytes (inter-byte) read the Clocking in Native Mode.

CLK_FROM_EXT

Input

Asynchronous

Inter-byte clock coming from a neighboring byte BITSLICE_CONTROL CLK_TO_EXT_NORTH or CLK_TO_EXT_SOUTH output. When no inter-byte clocking is used or only the CLK_TO_EXT_ pins are used, this pin must be pulled High.

CLK_TO_EXT_NORTH

Output

Asynchronous

Inter-byte clock to the CLK_FROM_EXT input of a neighboring byte BITSLICE_CONTROL block located above (north) of this output. Use of this pin is enabled by the EN_CLK_TO_EXT_NORTH attribute.

CLK_TO_EXT_SOUTH

Output

Asynchronous

Inter-byte clock to the CLK_FROM_EXT input of a neighboring byte BITSLICE_CONTROL block located below (south) of this output. Use of this pin is enabled by the EN_CLK_TO_EXT_SOUTH attribute.

PCLK_NIBBLE_IN

Input

Asynchronous

Inter-nibble strobe/clock from the other BITSLICE_CONTROL in the byte.

Each byte contains two nibbles and each nibble has a PCLK_NIBBLE_IN input.

Use of this input is enabled by the EN_OTHER_PCLK attribute.

NCLK_NIBBLE_IN

Input

Asynchronous

Inter-nibble strobe/clock from the other BITSLICE_CONTROL in the byte.

Each byte contains two nibbles and each nibble has a NCLK_NIBBLE_IN input.

Use of this input is enabled by the EN_OTHER_NCLK attribute.

PCLK_NIBBLE_OUT

Output

Asynchronous

Inter-nibble strobe/clock to the other BITSLICE_CONTROL in the byte.

Each byte contains two nibbles and each nibble has a PCLK_NIBBLE_OUT output. This signal must be connected to PCLK_NIBBLE_IN input of another nibble in the byte.

NCLK_NIBBLE_OUT

Output

Asynchronous

Inter-nibble strobe/clock to the other BITSLICE_CONTROL in the byte.

Each byte contains two nibbles and each nibble has a NCLK_NIBBLE_OUT output. This signal must be connected to a NCLK_NIBBLE_IN input of another nibble in the byte.

The following RX/TX_BIT_CTRL_OUT and RX/TX_BIT_CTRL_IN pins are 40-bit bus connections between the BITSLICE_CONTROL and RXTX_BITSLICE, RX_BITSLICE, or TX_BITSLICE used. Each of these 40-bit buses carries data, clocks, RIU, and status signals between the BITSLICE_CONTROL and bit slices.

When an RXTX_BITSLICE, RX_BITSLICE, or TX_BITSLICE is used, these buses must be connected to the appropriate BITSLICE_CONTROL input and output bus (This Figure).

Example:

When RX_BITSLICE_0 is used, RX/TX_BIT_CTRL_OUT must connect to the BITSLICE_CONTROL RX/TX_BIT_CTRL_IN0 and the RX/TX_BIT_CTRL_IN buses must connect to the BITSLICE_CONTROL RX/TX_BIT_CTRL_OUT0 buses.

These buses are made of dedicated routing between the BITSLICE_CONTROL and bit slices.

RX_BIT_CTRL_OUTx[39:0]

Output

N/A

Output bus connected to the RX_BIT_CTRL_IN from the bit slice.

RX_BIT_CTRL_INx[39:0]

Input

N/A

Input bus connected to the RX_BIT_CTRL_OUT from the bit slice.

TX_BIT_CTRL_OUTx[39:0]

Output

N/A

Output bus connected to the TX_BIT_CTRL_IN from the bit slice.

TX_BIT_CTRL_INx[39:0]

Input

N/A

Input bus connected to the TX_BIT_CTRL_OUT from the bit slice.

TX_BIT_CTRL_OUT_TRI[39:0]

Output

N/A

Output bus to the TX_BITSLICE_TRI.

TX_BIT_CTRL_IN input bus.

TX_BIT_CTRL_IN_TRI[39:0]

Input

N/A

Input bus from the TX_BITSLICE_TRI.

TX_BIT_CTRL_OUT output bus.