Bank Overview

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Each I/O bank contains 52 pins that can be used for input, output, or bidirectional operations using single-ended standards appropriate for the bank. The I/O banks can be either high-range (HR) or high-performance (HP) I/O banks. Up to 48 of these pins can be configured as up to 24 differential signaling pin pairs with signaling standards appropriate for either an HR I/O or an HP I/O bank. The logic associated with each single-ended pin is known as a bit slice, and the differential pin pairs are referenced as a master bit slice for the _P pin and slave bit slice for the _N pin throughout this user guide.

An overview of each bank is shown in This Figure. The input/output control block bit slices can be programmed using either component primitives as in previous generations of Xilinx® devices or, where maximum performance is required, configured using native PHY primitives. Both mechanisms are discussed in this chapter.

Figure 2-1:      Bank Overview

X-Ref Target - Figure 2-1

X16003-bank-overview.jpg

 

TIP:   Native mode designs have additional restrictions. The High-Speed SelectIO wizard (HSSIO-Wiz) automatically sets up all required settings and checks the design rules to ensure a working design. Xilinx recommends using the HSSIO-Wiz for Native mode designs.

The two available PLLs are associated with bit slices in the same I/O bank. Each PLL has a dedicated high-speed clock connection to the controller of the bit slices and two extra outputs that can be used for application clocks for logic placed in the clock area that the I/O bank covers. The mixed-mode clock manager (MMCM) can be used as a clock source for the controller of the bit slices in the I/O bank and logic placed in the clock area the I/O bank covers, but the MMCM can also be used as a clock source for I/O banks and logic in the entire FPGA.

 

TIP:   Use the PLLs placed in the clock area behind the I/O bank for applications requiring high performance and low jitter. The MMCM could be used for slower applications requiring clocking in multiple I/O banks and clock areas.

Use the following XDC constraint if the clock input is not part of the I/O bank used for the interface that needs to be designed.

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets <clock_net_name>]

This constraint causes Vivado® tools to issue a warning instead of stopping with an error.

 

TIP:   In Native mode, the high-speed clock output of the PLL connects to the BITSLICE_CONTROL.PLL_CLK inputs over dedicated routing (without a clock buffer). So always place the PLL in the clock area joining the I/O bank of the interface. The input clock buffer can be placed in a different I/O bank while using the XDC constraint.

Clock buffers must be used when an MMCM is used to clock a Native or Component mode interface. Although the best solution is to place the MMCM near the constructed I/O interface, the MMCM can be placed in a different clock area than the one adjacent to the I/O bank used. The clocks for the I/O interface are then distributed by clock buffers and clock routing.

Each bank is subdivided into four byte groups, each group containing 13 I/O pins as shown in This Figure. Each byte group is further sub-divided into two nibble groups, as shown in This Figure. The 3-state control bit slice blocks and upper and lower nibble control blocks are only relevant when using the Native mode, and are further described in subsequent sections. All bit slices can be used for either single-ended or differential signaling, with the exception of BITSLICE_12 (BITSLICE_6 in the upper nibble), which is only intended for single-ended signaling. Any single-ended clocks for use with the bit slices should use BITSLICE_0 of a nibble, and any differential clocks should use BITSLICE_0 (P-side) and BITSLICE_1 (N-side) of a nibble. Other pins can be used for clocks that require access to global clocking resources, as described in the UltraScale Architecture Clocking Resource User Guide (UG572) [Ref 9].

Figure 2-2:      Byte Group Overview

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X16004-byte-group-overview.jpg

The two central byte groups (1 and 2) each contain clocks quad byte clock (QBC) and global clock (GC)-capable input pins or pin pairs. The QBC pins can be used as capture clock inputs for the nibble or byte group they are placed in, but they can also deliver a capture clock through a dedicated clock backbone to all other nibbles and byte groups in the I/O bank. The GC pins are clock inputs that can drive MMCM and/or PLL primitives. Some of these clock-capable inputs have dual function capabilities—QBC and GC. The upper and lower byte groups each contain dedicated byte clock (DBC) clock-capable input pins (pin pairs) that can be used for clocking inside the byte group but do not have the capability to drive a capture clock to other byte groups in the I/O bank or to drive MMCM or PLLs in the I/O bank.

Additional restrictions might apply to BITSLICE_0 for the upper nibble and lower nibble.

Note:   BITSLICE_0 for the upper nibble is the equivalent of BITSLICE_6 for a byte group. See the example I/O bank (bank 44 of XCKU040FFVA1156) in This Figure for an explanation of bitslice numbering within a byte and nibble.

When using RX_BITSLICE or RXTX_BITSLICE, inter-byte clocking might affect BITSLICE_0 availability.

If using inter-byte clocking (QBC) from a nibble in one byte (source) to a nibble in another byte (sink), the nibble in the sink byte must always include BITSLICE 0 and its DATA_TYPE set to DATA.

For Receive serial mode applications, every nibble must include BITSLICE 0 and its DATA_TYPE set to SERIAL.

See Clocking in Native Mode for additional details.

IDELAY/ODELAY and RX_BITSLICE/TX_BITSLICE/RXTX_BITSLICE support TIME mode, which provides more precise delays by continuously adjusting the alignment. When TIME mode is used for IDELAY/ODELAY and native primitives, BITSLICE_0 is used during an initial calibration process. In the case of IDELAY/ODELAY, this initial calibration process is completed when RDY (IDELAYCTRL) is asserted high. Component logic connected to BITSLICE_0 might not be available during the initial calibration in these conditions:

IDELAY/ODELAY in TIME mode

RX_BITSLICE/TX_BITSLICE/RXTX_BITSLICE in TIME mode

Vivado will issue an error message to indicate input routing and logic associated with BITSLICE_0 within a nibble will be unavailable during the BISC operation. If these restrictions do not affect a design, the DRC can be disabled with the following constraint:

set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports <name>]

As BITSLICE_0 is used for calibration for the TIME mode, all other bit slices within the nibble will not be available until after calibration has completed when IDELAY/ODELAY are in TIME mode.

Each of the UltraScale™ FPGA I/O banks, bytes, and nibbles have the same setup. This Figure shows an example of a pin setting of I/O bank 44 of a XCKU040FFVA1156 FPGA. The setup shown can be applied to all I/O banks over the entire FPGA family. Using This Figure simplifies making pin nibble, byte, and I/O bank pin assignments.

Figure 2-3:      Example I/O Bank (Bank 44 of XCKU040FFVA1156)

X-Ref Target - Figure 2-3

X16263-io-bank-44-of-xcku040ffva1156.jpg