Bidirectional Signaling Using Component Mode

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

All 52 pins in a bank are capable of bidirectional operation using the same component primitives.

For bidirectional signaling with 3-state support, for the output and 3-state path use the solutions as discussed in ODDRE1. Note the 3-state path driving the T input for the IOBUF does not support simple registered outputs such as FDCE/FDPE/FDRE/FDSE. Registers for FDCE/FDPE/FDRE/FDSE for the 3-state path are implemented in internal logic.

For designs using an OSERDES, This Figure shows an example bidirectional pin with IDELAY and ODELAY. The OSERDES only supports combinatorial 3-state controls for the T input of the IOBUF.

Figure 2-30:      Bidirectional Signaling Using IDELAY/ODELAY with ISERSDES and OSERDES

X-Ref Target - Figure 2-30

X19512-bidi-signaling-using-idelay-odelay.jpg

Note:   When using bidirectional interfaces, the delay cascades are not available. For all other solutions, Native Primitives must be used.

Bidirectional support varies by I/O bank. Table: Bidirectional Support by I/O Bank lists the recommended bidirectional logic. When unsupported, the Vivado tool can borrow resources from additional I/Os.

Table 2-19:      Bidirectional Support by I/O Bank

Input Datapath

Output Datapath

Tristate Control

I/O Banks

Fabric Logic

Fabric Logic

Fabric Logic

HRIO/HDIO/HPIO

IFD

OFD

Fabric Logic

HRIO/HDIO/HPIO

IFD

OFD

OFD

HDIO

IDDRE1

ODDRE1

Fabric Logic

HRIO/HPIO

IDDE1

ODDRE1

ODDRE1

HRIO/HPIO

ISERDES3

OSERDESE3

Fabric Logic

HRIO/HPIO

ISERDES3

OSERDESE3

OSERDESE3

Not supported