When a bank contains two different interfaces, the used BITSLICE_CONTROLs within the bank share common control signals requiring the Native Mode Bring-up to start at the same time. Each interface can complete the bring-up sequence at different times. The High-Speed SelectIO wizard must also be modified to ensure the critical steps of the bring-up sequence are synchronized between the interfaces.
This Figure shows an example design that uses two different interfaces with separate RIU_CLK connections. When sharing a bank, the RIU_CLKs should not vary by more than 4x. For example, if RIU_CLK1 is 200 MHz, then RIU_CLK2 must be at least 50 MHz.
As a synchronous state machine, the input data should use the same clock as the state machine. For example, the LOCKED (PLL) signals for both interfaces must be ANDed together and resynchronized to the interface's RIU_CLK source. Interface 1 should use the RIU_CLK1 clock domain and interface 2 uses RIU_CLK2.
Each bank contains an RST_SEQ_DONE status signal. To determine when all of the banks are ready, the RST_SEQ_DONE from all of the interfaces should be logically ANDed to create an interface ready (INTF_RDY) signal. The INTF_RDY should be synchronized to the APP_CLK and used to control TBYTE_IN[3:0] for designs using TX_BITSLICE. When using the High-Speed SelectIO wizard, the tri_tbyte#[3:0] inputs should be connected to INTF_RDY signal. For designs targeting RX_BITSLICE, the FIFO_RD_EN should only be used after the entire interface is ready and INTF_RDY has gone High.
Note: Use the inverted FIFO_EMPTY signal of the used bit slice farthest away from the bit slice receiving the clock and thus generating the FIFO_WRCLK_OUT through an optional flip-flop to all FIFO_RD_EN inputs of used bit slices. Farthest means the bit slice at the end of the clock backbone. See the FIFO Function section in Native Primitives.