Bring-up for an Interface Using Multiple Banks

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

When an interface spans multiple banks, the clocking and bring-up sequence for each bank must be modified to ensure the interfaces start up correctly. When using the High-Speed SelectIO wizard, each bank can be customized by running the HSSIO-Wiz separately and selecting Enable Ports to Connect Multiple Interfaces. This Figure shows an interface that spans two banks. An application clock (APP_CLK) is used for loading data into the TX_BITSLICE. As shown in This Figure, the TX_BITSLICE uses the dedicated clocking from the PLL for the transmit clock. The dedicated PLL clock provides optimal performance for the TX_BITSLICE. For RX_BITSLICE, the APP_CLK is given as FIFO_RD_CLK to read the data from FIFO.

Figure 2-62:      TX_BITSLICE Application Clock

X-Ref Target - Figure 2-62

X19014-tx_bitslice-application-clock.jpg

The High-Speed SelectIO wizard can use CLKOUT0/CLKOUT1 for the application clock which can be used when a single bank is used.

In the case of multiple bank interfaces (This Figure), a single clock source is used to drive the APP_CLK for each of the High-Speed SelectIO wizard cores. Consequently CLKOUT0/CLKOUT1 should not be connected.

Figure 2-63:      Multi-bank Clocking

X-Ref Target - Figure 2-63

X19015-multiple-interfaces-in-shared-bank.jpg

The High-Speed SelectIO wizard uses the RIU_CLK for the Reset State Machine. To ensure multi-bank interfaces are aligned, all of the banks should be reset at the same time. The LOCKED outputs from each of the PLLs should be synchronized to the RIU_CLK domain and logically ANDed together. These changes allow the state machines to be brought up together.

Each bank contains an RST_SEQ_DONE status signal. To determine when all of the banks are ready, the RST_SEQ_DONE from all of the interfaces should be logically ANDed to create an interface ready (INTF_RDY) signal. The INTF_RDY should be synchronized to the APP_CLK and used to control TBYTE_IN[3:0] for designs using TX_BITSLICE. When using the High-Speed SelectIO wizard, the tri_tbyte#[3:0] inputs should be connected to INTF_RDY signal. For designs targeting RX_BITSLICE, the FIFO_RD_EN should only be used after the entire interface is ready and INTF_RDY has gone High.

Note:   Use the inverted FIFO_EMPTY signal of the used bit slice farthest away from the bit slice receiving the clock and thus generating the FIFO_WRCLK_OUT through a flip-flop to all FIFO_RD_EN inputs of used bit slices. Farthest means the bit slice at the end of the clock backbone. See the FIFO Function section in Native Primitives.

When using the High-Speed SelectIO wizard, the INTF_RDY is internally synchronized to APP_CLK.

This is a summary of multi-bank requirements.

Multi-bank clocking changes:

°PLLs for each of the High-Speed SelectIO wizard cores should be driven from a single MMCM clock source to minimize skews between the PLLs. As a result, if three banks were to be used, the MMCM should be placed in the middle I/O bank. Minimizing the clock skews to the different PLLs is more critical than controlling the input clock routing for the MMCM.

°Application clock (APP_CLK) for each core must be updated to use the MMCM clock for multi-bank clocking.

Reset State Machine

°All PLLs and reset state machines should be reset at the same time.

°LOCKED outputs from all banks must be combined and synchronized to the RIU clock domain. Because the LOCKED signal is an input into the reset state machine, which is driven by the RIU clock domain, the combined multi-bank LOCKED signal must also be in the RIU clock domain.

°The application must wait for RST_SEQ_DONE from all banks before enabling the application (INTF_RDY). This signal should be synchronized to the application clock domain and control TBYTE_IN[3:0] for transmit applications or FIFO_RD_EN for receive applications.