Built-in Self-Calibration

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The built-in self-calibration (BISC) block is a digital control and calibration block inside the BITSLICE_CONTROL component based on a delay-locked loop (DLL) circuit and on a digital delay-line phase detector. The BISC controller calculates the desired tap values for the digital delay lines and keeps track of these values over voltage and temperature drift. By default, when the correct attributes are set after instantiation of the BITSLICE_CONTROL primitive, the BISC controller reports the status of DLY and VTC back to the logic after tuning the used delay lines (This Figure).

The BISC controller registers can also be accessed through the register interface unit (RIU). This give you full control over the BISC process. It is possible to initiate or influence a BISC run and read back or change registers the BISC controller has filled or modified.

The EN_VTC signal of any connected bit slice with a TIME delay that needs to be calibrated must have an individual EN_VTC signal asserted (High) during initial self-calibration and after DLY_RDY is High during VT calibration.

Figure 2-72:      Block Diagram of the BISC Controller and Connections

X-Ref Target - Figure 2-72

X16047-block-diag-of-the-bisc-controller-and-conns.jpg