In Component mode, the ISERDES/OSERDES component clocks must be driven from global clocking. The clocks can be sourced from any of the following global clock resources:
•Clock-capable I/O driving a BUFGCE or BUFGCE_DIV
•MMCM driving a BUFGCE or BUFGCE_DIV
•PLL driving a BUFGCE/BUFGCE_DIV
A typical Component mode receive and transmit clocking topology using SerDes is shown in This Figure.
In the receive circuit, the ISERDESE3 is configured with the FIFO enabled (attribute FIFO_ENABLE = TRUE). The incoming serialized data is captured in the ISERDESE3 using a high-speed clock sourced from a clock-capable I/O driving a BUFGCE, connected to the ISERDESE3 CLK/CLK_B pins. The deserialized data is read out by a divided version of the high-speed clock, with the division factor relating to the deserialized width (SerDes attribute DATA_WIDTH). For example, with DATA_WIDTH = 8, the clock is divided by 4, assuming it is a DDR transmission. The circuit in This Figure uses a BUFGCE_DIV to perform the division. The divided clock is connected to both the CLKDIV and FIFO_RD_CLK of the ISERDESE3. An alternative uses a capture circuit with a disabled ISERDESE3 FIFO (attribute FIFO_ENABLE = FALSE). In this arrangement (not shown), the FIFO_RD_CLK signal should not be connected, although the CLKDIV signal must still be in place. The deserialized data is output from the ISERDESE3 using an automatic, internally generated, divided clock. In this mode, static timing analysis using the Vivado design tools shows the ISERDESE3 read timing relative to this internally generated divided clock.
The Component mode transmit circuit is also shown in This Figure. The parallel/deserialized transmit data is sampled at the OSERDESE3 data inputs using a divided clock that must be supplied to the OSERDESE3 CLKDIV input. Like the ISERDESE3, the divided clock can be generated using a BUFGCE_DIV (as shown), or alternatively using an MMCM or PLL. The serialized data is output from the OSERDESE3 using the supplied high-speed clock connected to the OSERDESE3 CLK input. When the IDDRE1 and ODDRE1 are used instead of the ISERDESE3 and OSERDESE3 (for a deserialized width of 2), connect the CLK input to the high-speed global clock. No divided clock is necessary. Although not shown in This Figure, it is also possible to insert an IDELAYE3 in the receive circuit and an ODELAYE3 in the transmit circuit between the IOB and the SerDes.
In This Figure, a single clock source from an MMCM output drives the BUFG and BUFGCE_DIV to minimize clock skews. In this situation, clock skews are analyzed by Vivado.
Note: When using the BUFGCE_DIV, the divided clock is not guaranteed to be aligned, which is why fabric logic should be driven by the BUFGCE_DIV.
In some situations, multiple clock outputs from the MMCM are required see This Figure. Skews are introduced by the MMCM outputs, making clock skew hard to meet. To ensure clock skews are correctly calculated, define a CLOCK_DELAY_GROUP for the clock buffers.
set_property CLOCK_DELAY_GROUP <Clock Delay Group Name> [get_nets-of_objects [get_pins <BUFG CLKOUT1 Instance>/O] ]
set_property CLOCK_DELAY_GROUP <Clock Delay Group Name> [get_nets-of_objects [get_pins <BUFG CLKOUT2 Instance>/O] ]
When using IDELAY in TIME mode, the CLK input (IDELAY) should be connected to the low-speed divided clock (CLKDIV) for the ISERDES as shown in This Figure. The same is true for ODELAY, such that the CLK (ODELAY) should be connected to CLKDIV (OSERDES).
The reference clock for IDELAYCTRL is the reference clock for all IDELAYs and ODELAYs that are used in TIME mode and is typically a different clock source. Because each nibble is controlled by a single IDELAYCTRL, all of the IDELAYs and ODELAYs within that nibble must set the REFCLK_FREQUENCY to the frequency of the clock connected to REFCLK to ensure the delays.