DCI Cascading

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The HP I/O banks using DCI I/O standards have the option of deriving the DCI impedance values from another HP I/O bank. As shown in This Figure, a digital control bus is internally distributed throughout the bank to control the impedance of each I/O.

Figure 1-7:      DCI Use within a Bank

X-Ref Target - Figure 1-7

X16065-dci-use-within-a-bank.jpg

With DCI cascading, one I/O bank (the master bank) must have its VRP pin connected to an external reference resistor. Other I/O banks in the same HP I/O bank column (slave banks) can use DCI standards with the same impedance as the master bank, without connecting the VRP pin on these slave banks to an external resistor. DCI impedance control in cascaded banks is received from the I/O master bank.

This Figure shows DCI cascading support over multiple I/O banks. Bank B is the master I/O bank, and Banks A and C are considered slave I/O banks.

Figure 1-8:      DCI Cascading Supported over Multiple I/O Banks

X-Ref Target - Figure 1-8

X16066-dci-cascading-supported-over-multiple-io-banks.jpg

The guidelines when using DCI cascading are as follows:

DCI cascading is only available through a column of HP I/O banks

The master and slave SelectIO technology banks must all reside on the same HP I/O column on the device and can span the entire column unless there is an interposer boundary.

DCI cascading cannot pass through the interposer boundaries of the larger UltraScale devices with stacked silicon interconnect (SSI) technology.

Master and slave I/O banks must have the same VCCO and VREF (if applicable) voltage.

I/O banks in the same HP I/O column that are not using DCI (pass-through banks) do not have to comply with the VCCO and VREF voltage rules for combining DCI settings.

DCI I/O banking compatibility rules must be satisfied across all master and slave banks.

To locate I/O banks that reside in the same I/O column, see the figures in the Die Level Bank Numbering Overview section of the UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) [Ref 3].

For specific information on implementing DCI cascading in a design, see DCI_CASCADE Constraint.

 

RECOMMENDED:   Unused banks must be powered up because leaving the VCCO pins of unused I/O banks floating reduces the level of ESD protection on these pins and the I/O pins in the bank. If the bank is unpowered, DCI can still be cascaded through the unpowered bank.

When DCI cascading is used, source and on-die input terminations have a bigger variation as compared to DCI used on a per bank basis without cascade. See the product’s data sheet for quantity [Ref 2].