DCI I/O Standard Support

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2023-08-31
Revision
1.15 English

DCI supports the standards shown in Table: All Supported DCI I/O Standards .

Table 1-6: All Supported DCI I/O Standards

LVDCI_18

HSTL_I_DCI

DIFF_HSTL_I_DCI

SSTL18_I_DCI

DIFF_SSTL18_I_DCI

LVDCI_15

HSTL_I_DCI_18

DIFF_HSTL_I_DCI_18

SSTL15_DCI

DIFF_SSTL15_DCI

HSLVDCI_18

HSTL_I_DCI_12

(UltraScale devices only)

DIFF_HSTL_I_DCI_12

(UltraScale devices only)

SSTL135_DCI

DIFF_SSTL135_DCI

HSLVDCI_15

SSTL12_DCI

DIFF_SSTL12_DCI

HSUL_12_DCI

DIFF_HSUL_12_DCI

POD12_DCI

DIFF_POD12_DCI

POD10_DCI

DIFF_POD10_DCI

To correctly use DCI:

1. V CCO pins must be connected to the appropriate V CCO voltage based on the I/O standards in that I/O bank.

2. Correct DCI I/O buffers must be used in the Vivado Design Suite either by using I/O standard attributes or instantiations in the hardware description language (HDL) code. The Vivado Design Suite automatically restricts the VRP pin from being used as an I/O when a VRP needs to be used as a reference.

3. DCI standards require connecting an external reference resistor to the multipurpose VRP pin. When this is required, that multipurpose pin cannot be used as a general-purpose I/O in the I/O bank using DCI or in the master I/O bank when cascading DCI. See the pinout tables for the specific pin locations. The VRP pin must be pulled to GND by a reference resistor. An exception to this requirement comes when cascading DCI in slave I/O banks because the VRP pin can be used as general-purpose I/O.

4. The value of the external reference resistor is fixed at 240 , terminated to GND.

5. Follow the DCI I/O banking rules:

a. V REF must be compatible for all of the inputs in the same I/O bank or in a group of I/O banks when using DCI cascade.

b. V CCO must be compatible for all of the inputs and outputs in the same I/O bank.

c. Impedances are no longer constrained by R VRP (240 W) . The DCI state machine calculates the appropriate scaling for controlled impedance drivers, and split and single-termination configurations using OUTPUT_IMPEDANCE and ODT attribute values.