UltraScale devices have dedicated registers in the ILOGIC block to implement input DDR registers. This feature is used by instantiating the IDDRE1 primitive. The IDDRE1 primitive supports these modes of operation:
The SAME_EDGE and SAME_EDGE_PIPELINED mode data is presented into the interconnect logic on the same clock edge. These modes are implemented using the DDR_CLK_EDGE attribute.
This Figure shows a block diagram of the IDDRE1 primitive. Table: IDDRE1 Ports lists the IDDRE1 ports and Table: IDDRE1 Attributes lists the IDDRE1 attributes.
To ensure output registers are forced to use the IOB resources, use the following syntax in the XDC:
set_property IOB TRUE [get_ports portname]