DDR Outputs (ODDRE1)

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

UltraScale devices have registers in the OLOGIC block to implement output DDR registers for both data and 3-state control. When data and 3-state paths are both used in HD I/O, both data and 3-state control are required to either both use (or both not use) the output DDR register. For example, you cannot have a design that uses an output DDR register on the datapath without an output DDR register on the 3-state control path.

This feature is accessed when instantiating the ODDRE1 primitive. DDR multiplexing is automatic when using the ODDRE1. No manual control of the multiplexer select is needed. This control is generated from the clock.

There is only one clock input to the ODDRE1 primitive. Falling-edge data is clocked by a locally inverted version of the input clock.

The ODDRE1 primitive supports only the SAME_EDGE mode of operation. The SAME_EDGE mode allows designers to present both data inputs to the ODDRE1 primitive on the rising edge of the ODDRE1 clock, saving CLB and clock resources, and increasing performance. This mode is also supported for 3-state control. The timing diagram of the output DDR is shown in This Figure. This Figure shows a block diagram of the ODDRE1 primitive. The ODDRE1 block in HD bank differs from the XP bank in that SR pin deassertion occurs immediately with no register delay. Compared to simulation, ODDRE1 in HD banks comes out of reset 3 clock cycles early. Table: ODDRE1 Ports  lists the ODDRE1 ports and Table: ODDRE1 Attributes  lists the ODDRE1 attributes.

To ensure output registers are forced to use the IOB resources, use the following syntax in the XDC. For data:

set_property IOB TRUE [get_cell <cell_name>]

For tristate:

set_property IOB_TRI_REG value [get_cells <cell_name>]