UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
Release Date
1.14 English

The tap size of the ODELAYE3 primitive is defined in the UltraScale device data sheets as TODELAY_RESOLUTION (TIDELAY_RESOLUTION for IDELAYE3) [Ref 2]. If the DELAY_FORMAT is set to TIME, the delay line is calibrated, controlled, and maintained for voltage and temperature by the IDELAYCTRL component.

An IDELAYCTRL component must be used.

The REFCLK_FREQUENCY attribute must reflect the clock frequency applied to the IDELAYCTRL component.

The EN_VTC pin must be actively manipulated when the delay line is used in VARIABLE or VAR_LOAD mode. When FIXED mode is used, tie the EN_VTC pin High.

When the DELAY_FORMAT is set to COUNT, the delay line is not calibrated and is not maintained over voltage and temperature. Therefore:

Do not use an IDELAYCTRL component.

Leave the REFCLK_FREQUENCY attribute at the default value (300 MHz).

Tie the EN_VTC input pin Low.

°This pin ensures that calibration and VT maintenance logic in the ODELAYE3 is disabled.

The delay line must be used to represent an amount of taps.

°It does not matter how long the tap delay is; it is the amount of taps that is important.

°512 taps are available.

The CNTVALUEIN/OUT[8:0] values represent the amount of taps the delay line is set or tuned to.

Examples of how the DELAY_FORMAT attribute is used are provided in the mode paragraphs in the DELAY_TYPE Attribute.