DELAY_SRC Attribute

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

DELAY_SRC (This Figure) is set based on where the input to be delayed originates. When the input comes from an IOB, it should be set to IDATAIN. When the input comes from the interconnect logic, it should be set to DATAIN. When enabling the IDELAYE3, there is an additional insertion delay added because the signal must pass through a multiplexer. The delay associated with this multiplexer is the insertion delay. If an IDELAYE3 is used with a DELAY_VALUE = 0, the data still incurs an insertion delay to propagate through the delay element. This delay is accounted for in the Vivado Design Suite timing analysis.

Figure 2-17:      IDELAYE3 DELAY_SRC Diagram

X-Ref Target - Figure 2-17

X16017-idelaye3-delay_src-diag.jpg