DQS_BIAS

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

DQS_BIAS behaves as a logic holding mechanism for undriven pins in pseudo-differential (DIFF_SSTL, DIFF_HSUL, and DIFF_POD) buffers by weakly pulling the N side of the buffer to VCCO and the P side of the buffer to ground. For LVDS inputs, DQS_BIAS provides a DC bias of VCCO/2 to both the P and N sides of the buffer.

The allowed values for the DQS_BIAS attribute for applicable I/O standards are:

TRUE where DQS_BIAS = TRUE cannot be used in conjunction with the PULLTYPE attribute set to PULLUP, PULLDOWN, or KEEPER in the same port.

FALSE (default)

 

IMPORTANT:   Starting with Vivado Design Suite 2018.1, the DQS_BIAS attribute should be set on the port, not on the cell.

The DQS_BIAS attribute should be set on the port using the syntax:

set_property DQS_BIAS TRUE|FALSE [get_ports port_name]