Differences from Previous Generations

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

UltraScale devices support many of the same features supported in 7 series devices. However, there are some useful new features, along with changes to several existing features. These new features and changes include:

Each I/O bank contains 52 SelectIO interface pins. In some devices, there are some HR I/O mini-banks containing 26 SelectIO pins, each with their own independent power supply and VREF pin.

 

TIP:   All references in this user guide discussing HR I/O banks also apply to HR I/O mini-banks.

Support for pseudo-open-drain logic standards (POD).

Series output termination control is available in HP I/O banks for improved signal integrity and ease of board design.

Internal VREF level scan (HP I/O banks only). One dedicated external VREF pin per bank.

Pre-emphasis is available for the DDR4 standard in HP I/O banks and the LVDS TX standard in HP/HR I/O banks. Pre-emphasis reduces inter-symbol interference and minimizes the effects of transmission line losses.

Linear equalization on VREF-based receivers (in HP I/O banks) and differential receivers (in both HP and HR I/O banks) is available to overcome high-frequency losses through the transmission channel.

Receiver offset cancellation is available for some I/O standards to compensate for process variations (HP I/O banks only).

Digitally controlled impedance (DCI) is only available in HP I/O banks. DCI uses only one reference resistor per bank, 240W to GND on the VRP pin. The values of the driver or input termination are determined by the OUTPUT_IMPEDANCE and on-die termination (ODT) attributes, respectively.

VCCAUX_IO only supports a nominal voltage level of 1.8V.

A SLEW value of MEDIUM is supported in HP I/O banks.

The DCITERMDISABLE port can control both DCI and non-DCI on-die input termination features in HP I/O banks.

Where applicable, asserting IBUFDISABLE causes the input to the interconnect logic to be a 0. This is different from the resulting 1 after asserting IBUFDISABLE in 7 series devices.

The bit slice is effectively a physical layer (PHY) block that replaces and enhances the functionality of the Component mode primitives. This PHY block gives tighter control over timing and provides new features enabling higher data rate reception in UltraScale devices. See Native Primitives.

MIPI D-PHY transmitter and receiver functions are supported in the HP I/Os specific to the Virtex UltraScale+, Kintex UltraScale+, and Zynq UltraScale+ devices.