Differential HSTL Class II

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

This Figure shows a sample circuit illustrating a termination technique for differential HSTL (1.5V or 1.8V) with unidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.5V or 1.8V); they are not interchangeable (i.e., DIFF_HSTL_II_18 should only interface with DIFF_HSTL_II_18). Only HR I/O banks support the class-II standards (i.e., DIFF_HSTL_II_18 should only interface with DIFF_HSTL_II_18).

Figure 1-62:      Differential HSTL (1.5V or 1.8V) Unidirectional Termination

X-Ref Target - Figure 1-62

X16122-diff-hstl-1_5v-or-1_8v-uni-term.jpg

This Figure shows a sample circuit illustrating a termination technique for differential HSTL class-II (1.5V or 1.8V) with bidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.5V or 1.8V); they are not interchangeable (i.e., DIFF_HSTL_II_18 should only interface with DIFF_HSTL_II_18).

Figure 1-63:      Differential HSTL Class II (1.5V or 1.8V) Bidirectional Termination

X-Ref Target - Figure 1-63

X16123-diff-hstl-class-ii-1_5v-or-1_8v-bidi-term.jpg

Table: HSTL Class I Allowed Attributes and Table: Only Allowed Combinations for Bidirectional Configurations  list the supported attributes for the HSTL I/O standards. Support is implied for primitives that are derivatives of the primitives listed in these tables (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to the SelectIO Interface Primitives section for all supported derivatives.

Table 1-36:      HSTL Class I Allowed Attributes

Attributes

IBUF/IBUFE3/IBUFDS/IBUFDSE3

OBUF/OBUFT

IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3

HP I/O

HR I/O

HP I/O

HR I/O

HP I/O

HR I/O

Allowed Values

Default

Allowed Values

Default

Allowed Values

Default

Allowed Values

Default

Allowed Values

Default

Allowed Values

Default

IOSTANDARD

HSTL_I
HSTL_I_12
HSTL_I_18

HSTL_I
HSTL_I_18

HSTL_I
HSTL_I_12
HSTL_I_18

HSTL_I
HSTL_I_18

HSTL_I
HSTL_I_12
HSTL_I_18

HSTL_I
HSTL_I_18

SLEW

N/A

N/A

FAST
MEDIUM
SLOW

SLOW

FAST
SLOW

SLOW

FAST
MEDIUM
SLOW

SLOW

FAST
SLOW

SLOW

ODT

RTT_40
RTT_48
RTT_60
RTT_NONE

RTT_NONE

RTT_40
RTT_48
RTT_60
RTT_NONE

RTT_NONE

N/A

N/A

RTT_40
RTT_48
RTT_60
RTT_NONE
(1)

RTT_NONE

RTT_40
RTT_48
RTT_60
RTT_NONE

RTT_NONE

OUTPUT_
IMPEDANCE

N/A

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60

RDRV_48_48

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60
(1)

RDRV_48_48

N/A

IOSTANDARD

HSTL_I_DCI
HSTL_I_DCI_12
HSTL_I_DCI_18

N/A

HSTL_I_DCI
HSTL_I_DCI_12
HSTL_I_DCI_18

N/A

HSTL_I_DCI
HSTL_I_DCI_12
HSTL_I_DCI_18

N/A

SLEW

N/A

N/A

FAST
MEDIUM
SLOW

SLOW

N/A

FAST
MEDIUM
SLOW

SLOW

N/A

ODT

RTT_40
RTT_48
RTT_60
(2)

RTT_48

N/A

N/A

N/A

RTT_40
RTT_48
RTT_60
(1)(2)

RTT_48

N/A

OUTPUT_
IMPEDANCE

N/A

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60

RDRV_48_48

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60
(1)

RDRV_48_48

N/A

IOSTANDARD

DIFF_HSTL_I
DIFF_HSTL_I_12
DIFF_HSTL_I_18

DIFF_HSTL_I DIFF_HSTL_I_18

DIFF_HSTL_I
DIFF_HSTL_I_12
DIFF_HSTL_I_18

DIFF_HSTL_I
DIFF_HSTL_I_18

DIFF_HSTL_I
DIFF_HSTL_I_12
DIFF_HSTL_I_18

DIFF_HSTL_I
DIFF_HSTL_I_18

SLEW

N/A

N/A

FAST
MEDIUM
SLOW

SLOW

FAST
SLOW

SLOW

FAST
MEDIUM
SLOW

SLOW

FAST
SLOW

SLOW

ODT

RTT_40
RTT_48
RTT_60
RTT_NONE

RTT_NONE

RTT_40
RTT_48
RTT_60
RTT_NONE

RTT_NONE

N/A

N/A

RTT_40
RTT_48
RTT_60
RTT_NONE
(1)

RTT_NONE

RTT_40
RTT_48
RTT_60
RTT_NONE

RTT_NONE

OUTPUT_
IMPEDANCE

N/A

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60

RDRV_48_48

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60
(1)

RDRV_48_48

N/A

IOSTANDARD

DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_12 DIFF_HSTL_I_DCI_18

N/A

DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_12 DIFF_HSTL_I_DCI_18

N/A

DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_12 DIFF_HSTL_I_DCI_18

N/A

SLEW

N/A

N/A

FAST
MEDIUM
SLOW

SLOW

N/A

FAST
MEDIUM
SLOW

SLOW

N/A

ODT

RTT_40
RTT_48
RTT_60
(2)

RTT_48

N/A

N/A

N/A

RTT_40
RTT_48
RTT_60
(1)(2)

RTT_48

N/A

OUTPUT_
IMPEDANCE

N/A

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60

RDRV_48_48

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60
(1)

RDRV_48_48

N/A

Notes:

1.The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table: Only Allowed Combinations for Bidirectional Configurations .

2.ODT = RTT_NONE is not a valid setting for DCI I/O standards.

Table 1-37:      Only Allowed Combinations for Bidirectional Configurations 

OUTPUT_IMPEDANCE

ODT

RDRV_40_40 (40W)

RTT_40

RDRV_40_40 (40W)

RTT_60

RDRV_40_40 (40W)

RTT_NONE

RDRV_48_48 (48W)

RTT_48

RDRV_48_48 (48W)

RTT_NONE

RDRV_60_60 (60W)

RTT_40

RDRV_60_60 (60W)

RTT_60

RDRV_60_60 (60W)

RTT_NONE

Table: HSTL Class II Allowed Attributes  lists the supported attributes for the HSTL Class-II I/O standards. Support is implied for primitives that are derivatives of the primitives listed in Table: HSTL Class II Allowed Attributes  (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to the SelectIO Interface Primitives section for all supported derivatives.

Table 1-38:      HSTL Class II Allowed Attributes 

Attributes

IBUF/IBUFDS

OBUF/OBUFT

IOBUF/IOBUFDS

HP I/O

HR I/O

HP I/O

HR I/O

HP I/O

HR I/O

Allowed Values

Default

Allowed Values

Default

Allowed Values

Default

IOSTANDARD

N/A

HSTL_II
HSTL_II_18

N/A

HSTL_II
HSTL_II_18

N/A

HSTL_II
HSTL_II_18

SLEW

N/A

N/A

N/A

FAST
SLOW

SLOW

N/A

FAST SLOW

SLOW

ODT

N/A

RTT_40
RTT_48
RTT_60 RTT_NONE

RTT_NONE

N/A

N/A

N/A

RTT_40
RTT_48
RTT_60 RTT_NONE

RTT_NONE

IOSTANDARD

N/A

DIFF_HSTL_II
DIFF_HSTL_II_18

N/A

DIFF_HSTL_II
DIFF_HSTL_II_18

N/A

DIFF_HSTL_II DIFF_HSTL_II_18

SLEW

N/A

N/A

N/A

FAST
SLOW

SLOW

N/A

FAST
SLOW

SLOW

ODT

N/A

RTT_40
RTT_48
RTT_60 RTT_NONE

RTT_NONE

N/A

N/A

N/A

RTT_40
RTT_48
RTT_60
RTT_NONE

RTT_NONE