Differential POD

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2023-08-31
Revision
1.15 English

This Figure shows a sample circuit illustrating a termination technique for differential POD (1.0V, 1.2V) with unidirectional termination and with matched driver and receiver termination values. In a specific circuit, all drivers and receivers must be at the same voltage level (1.2V or 1.0V); they are not interchangeable (i.e., DIFF_POD12 should only interface with DIFF_POD12).

Figure 1-79: Differential POD with Unidirectional Signaling

X-Ref Target - Figure 1-79

X16139-diff-pod-w-uni-signaling.jpg

This Figure shows a sample circuit illustrating a termination technique for differential POD (1.0V or 1.2V) with bidirectional termination and with matched driver and receiver termination values. In a specific circuit, all drivers and receivers must be at the same voltage level (1.0V or 1.2V); they are not interchangeable (i.e., DIFF_POD10_DCI should only interface with DIFF_POD10_DCI).

Figure 1-80: Differential Pod with Bidirectional Signaling

X-Ref Target - Figure 1-80

X16140-diff-pod-w-bidi-signaling.jpg

Table: POD Allowed Attributes lists the allowed attributes for POD I/O standards. Support is implied for primitives that are derivatives of the primitives listed in Table: POD Allowed Attributes (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to the SelectIO Interface Primitives section for all supported derivatives.

Table 1-51: POD Allowed Attributes

Attributes

IBUF/IBUFE3/IBUFDS/
IBUFDSE3

OBUF/OBUFT

IOBUF/IOBUFE3/IOBUFDS/
IOBUFDSE3

HP I/O

HP I/O

HP I/O

Allowed Values

Default

Allowed Values

Default

Allowed Values

Default

IOSTANDARD

POD10
DIFF_POD10

POD10
DIFF_POD10

POD10
DIFF_POD10

SLEW

N/A

FAST
MEDIUM
SLOW

SLOW

FAST
MEDIUM
SLOW

SLOW

DQS_BIAS (5)

TRUE
FALSE

FALSE

N/A

TRUE
FALSE

FALSE

ODT

RTT_40, RTT_48
RTT_60, RTT_NONE

RTT_NONE

N/A

RTT_40, RTT_48
RTT_60, RTT_NONE
(1)

RTT_NONE

OUTPUT_
IMPEDANCE

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60

RDRV_40_40

RDRV_40_40
RDRV_48_48
RDRV_60_60
(1)

RDRV_40_40

IOSTANDARD

POD10_DCI
DIFF_POD10_DCI

POD10_DCI
DIFF_POD10_DCI

POD10_DCI
DIFF_POD10_DCI

SLEW

N/A

FAST
MEDIUM
SLOW

SLOW

FAST
MEDIUM
SLOW

SLOW

DQS_BIAS (5)

TRUE
FALSE

FALSE

N/A

TRUE
FALSE

FALSE

ODT

RTT_40
RTT_48
RTT_60
(2)

RTT_40

N/A

RTT_40
RTT_48
RTT_60
(1) (2)

RTT_40

OUTPUT_
IMPEDANCE

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60

RDRV_40_40

RDRV_40_40
RDRV_48_48
RDRV_60_60
(1)

RDRV_40_40

IOSTANDARD

POD12
DIFF_POD12

POD12
DIFF_POD12

POD12
DIFF_POD12

SLEW

N/A

FAST
MEDIUM
SLOW
(4)

SLOW

FAST
MEDIUM
SLOW
(3)

SLOW

PRE_EMPHASIS

N/A

RDRV_240
RDRV_NONE
(4)

RDRV_NONE

RDRV_240 RDRV_NONE (3)

RDRV_NONE

EQUALIZATION

EQ_LEVEL0, EQ_LEVEL1,
EQ_LEVEL2, EQ_LEVEL3,
EQ_LEVEL4, EQ_NONE

EQ_NONE

N/A

EQ_LEVEL0, EQ_LEVEL1,
EQ_LEVEL2, EQ_LEVEL3,
EQ_LEVEL4, EQ_NONE

EQ_NONE

OFFSET_CNTRL

CNTRL_NONE
FABRIC

CNTRL_NONE

N/A

CNTRL_NONE
FABRIC

CNTRL_NONE

DQS_BIAS (5)

TRUE
FALSE

FALSE

N/A

TRUE
FALSE

FALSE

ODT

RTT_40
RTT_48
RTT_60
RTT_NONE

RTT_NONE

N/A

RTT_40
RTT_48
RTT_60
(RTT_NONE) (3)

RTT_NONE

OUTPUT_
IMPEDANCE

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60 (4)

RDRV_40_40

RDRV_40_40
RDRV_48_48
RDRV_60_60 (3)

RDRV_40_40

IOSTANDARD

POD12_DCI
DIFF_POD12_DCI

POD12_DCI
DIFF_POD12_DCI

POD12_DCI
DIFF_POD12_DCI

SLEW

N/A

FAST
MEDIUM
SLOW (4)

SLOW

FAST
MEDIUM
SLOW (3)

SLOW

PRE_EMPHASIS (6)

N/A

RDRV_240 RDRV_NONE (4)

RDRV_NONE

RDRV_240 RDRV_NONE (3)

RDRV_NONE

EQUALIZATION

EQ_LEVEL0, EQ_LEVEL1,
EQ_LEVEL2, EQ_LEVEL3,
EQ_LEVEL4, EQ_NONE

EQ_NONE

N/A

EQ_LEVEL0, EQ_LEVEL1,
EQ_LEVEL2, EQ_LEVEL3,
EQ_LEVEL4, EQ_NONE

EQ_NONE

OFFSET_CNTRL

CNTRL_NONE
FABRIC

CNTRL_NONE

N/A

CNTRL_NONE
FABRIC

CNTRL_NONE

DQS_BIAS (5) (7)

TRUE
FALSE

FALSE

N/A

TRUE
FALSE

FALSE

ODT

RTT_40
RTT_48
RTT_60 (2)

RTT_40

N/A

RTT_40
RTT_48
RTT_60 (2) (3)

RTT_40

OUTPUT_
IMPEDANCE

N/A

RDRV_40_40
RDRV_48_48
RDRV_60_60 (4)

RDRV_40_40

RDRV_40_40
RDRV_48_48
RDRV_60_60 (3)

RDRV_40_40

Notes:

1. The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table: Only Allowed Combinations for Bidirectional Configurations .

2. ODT = RTT_NONE is not a valid setting for DCI I/O standards.

3. The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE), ODT, and PRE_EMPHASIS are listed in Table: Allowed Combinations of OUTPUT_IMPEDANCE, ODT, and PRE_EMPHASIS .

4. The combinations allowed of driver output impedance (OUTPUT_IMPEDANCE) and PRE_EMPHASIS are listed in Table: Allowed Combinations of OUTPUT_IMPEDANCE and PRE_EMPHASIS .

5. Only applicable to DIFF_POD I/O standards.

6. This attribute has to be used in conjunction with ENABLE_PRE_EMPHASIS to enable the pre-emphasis function.

7. This is read-only on the primitive. The DQS_BIAS attribute is set on the I/O port rather than the primitive.

Table: Allowed Combinations of OUTPUT_IMPEDANCE, ODT, and PRE_EMPHASIS and Table: Allowed Combinations of OUTPUT_IMPEDANCE and PRE_EMPHASIS lists the allowed combinations of attributes for POD I/O standards.

Table 1-52: Allowed Combinations of OUTPUT_IMPEDANCE, ODT, and PRE_EMPHASIS

OUTPUT_IMPEDANCE

SLEW

ODT

PRE_EMPHASIS

RDRV_40_40 (40 )

SLOW, MEDIUM, FAST

RTT_40

RDRV_NONE

RDRV_40_40 (40 )

SLOW, MEDIUM, FAST

RTT_60

RDRV_NONE

RDRV_40_40 (40 )

SLOW, MEDIUM, FAST

RTT_NONE

RDRV_NONE

RDRV_48_48 (48 )

SLOW, MEDIUM, FAST

RTT_48

RDRV_NONE

RDRV_48_48 (48 )

SLOW, MEDIUM, FAST

RTT_NONE

RDRV_NONE

RDRV_60_60 (60 )

SLOW, MEDIUM, FAST

RTT_40

RDRV_NONE

RDRV_60_60 (60 )

SLOW, MEDIUM, FAST

RTT_60

RDRV_NONE

RDRV_60_60 (60 )

SLOW, MEDIUM, FAST

RTT_NONE

RDRV_NONE

RDRV_40_40 (40 )

FAST

RTT_40

RDRV_240

RDRV_40_40 (40 )

FAST

RTT_60

RDRV_240

RDRV_40_40 (40 )

FAST

RTT_NONE

RDRV_240

Table 1-53: Allowed Combinations of OUTPUT_IMPEDANCE and PRE_EMPHASIS

OUTPUT_IMPEDANCE

SLEW

PRE_EMPHASIS

RDRV_40_40 (40 )

SLOW, MEDIUM, FAST

RDRV_NONE

RDRV_48_48 (48 )

SLOW, MEDIUM, FAST

RDRV_NONE

RDRV_60_60 (60 )

SLOW, MEDIUM, FAST

RDRV_NONE

RDRV_40_40 (40 )

FAST

RDRV_240