Extended Delay Control Signals

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Further information on the CE_EXT, CLK_EXT, EN_VTC_EXT, INC_EXT, RST_DLY_EXT, LOAD_EXT, CNTVALUEIN_EXT[8:0], and CNTVALUEOUT_EXT[8:0] signals is presented in this section.

In an RX_BITSLICE, the input delay line can be extended with the output delay line. To do this, the CASCADE attribute must be set to TRUE. When this is the case, all ports with extension _EXT must be used.

If CASCADE = FALSE, all ports with extension _EXT must be tied to ground (GND).

When the RX_BITSLICE is using the cascaded delay (attribute CASCADE = TRUE), then the output of the RX_BITSLICE input delay is connected to the input of the TX_BITSLICE (not used) output delay line. The output of the output delay line in the unused TX_BITSLICE is connected to the input of the deserializer logic in the RX_BITSLICE shown in This Figure. This effectively doubles the length of the delay line. Control of both delay lines is done through the control ports of each of the delays. The control ports of the output delay line are named with the _EXT extension. The function of the control ports of both delay lines is the same.

Figure 2-49:      Extended Delay Control Signals

X-Ref Target - Figure 2-49

X16319-extended-delay-control-signals.jpg

When DELAY_TYPE is FIXED, the input delay line and output delay line (extended or _EXT) control signals can be tied off to ground (GND) with the exception of EN_VTC and EN_VTC_EXT. When the delay lines are used in TIME mode, both pins must be tied to VCC and/or actively manipulated. When the delay lines are used in COUNT mode, both pins should be tied to ground (GND).

When the DELAY_TYPE is VARIABLE or VAR_LOAD:

If DELAY_FORMAT = TIME, the attribute DELAY_VALUE_EXT for the cascaded delay must have a delay that is equal to the master DELAY_VALUE attribute. For example, a total required delay of 1.5 ns is split between a 0.75 ns DELAY_VALUE_EXT and a 0.75 ns DELAY_VALUE. After BISC completes, the master and cascaded delay lines can have different values.

When configured in VAR_LOAD mode, the input delay line and the extended output delay line tap delay values should be loaded for both components separately using LOAD and LOAD_EXT with values set by CNTVALUEIN and CNTVALUEIN_EXT, respectively. They can have different values.

When configured in VARIABLE or VAR_LOAD modes, the CE/INC and CE_EXT/INC_EXT must each be incremented/decremented. The functional requirements for controlling these signals are the same as described for non-cascaded mode.

Note:   CASCADE = TRUE supports legacy design approaches that required the use of IDELAY to find the center of a UI for clock placement, and the amount of IDELAY can be up to 2.5 ns.

 

RECOMMENDED:   For better signal integrity and more robust eye sampling at higher data rates, Xilinx strongly recommends the use of BISC and its QTR Delays for finding and maintaining the center of a UI and avoid using IDELAYs for sweeping.

Note:   CASCADE = TRUE supports legacy designs where the use of IDELAY up to 2.5 ns is needed. Due to the nature of the cascaded delays and the additional delay taps, performance will degrade. Use the alignment associated with BISC and adjust the strobe clocks using PQTR/NQTR delay adjustments (RIU) for optimal performance.