The receiver of each RXTX_BITSLICE and thus RX_BITSLICE has an 8-deep shallow FIFO.
The deserialized 4-bit or 8-bit data is written using the FIFO_WR_CLK domain in the bit slice-generated clock (FIFO_WR_CLK) in the FIFO.
The FIFO writes the 4-bit or 8-bit deserialized data on the rising edge of FIFO_WR_CLK. The FIFO can be read after interpretation of some FIFO status signals from the FPGA logic side. In this way, the FIFO performs the role of clock domain crossing element. See more about the FIFO in FIFO Function .