FIFO Function

UltraScale Architecture SelectIO Resources User Guide (UG571)

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The FIFO is controlled by the following signals; FIFO_RD_CLK, FIFO_RD_EN, FIFO_EMPTY, and FIFO_WRCLK_OUT. Data from the FIFO is available at the Q[7:0] pins. The attributes controlling the FIFO behavior are RX_DATA_WIDTH and FIFO_SYNC_MODE. All of these are discussed in Table: RXTX_BITSLICE Ports and Table: RXTX_BITSLICE Attributes.

RX_DATA_WIDTH is an attribute acting for the entire receiver. When set to 4, the FIFO passes data out at pins Q[3:0] and a signal mimicking the serial input of the receiver is available at the Q5 pin. If RX_DATA_WIDTH is 8, the FIFO passes 8-bit data and the mimicked serial data output is not available. This Q5 serial data is only supported for RX_BITSLICE and RXTX_BITSLICE. ISERDES is not supported.

Set FIFO_SYNC_MODE to FALSE to use the FIFO as a clock domain crossing element. This mode allows data captured from the interface clock domain to successfully cross over to the interconnect logic clock domain(s). The typical latency through the FIFO is equal to two clock cycles (three when counting the extra FIFO enable cycles), but depending on the design, the latency can also be eight read clock cycles. Table: Behavior of the Clock and Control Inputs of the FIFO describes the behavior of the clock and control inputs of the FIFO.

Table 2-21:      Behavior of the Clock and Control Inputs of the FIFO

Clock or Control Input



This clock can be used as a read clock for the FIFO. Clocks to capture the data are generated inside the BITSLICE_CONTROL and RXTX_BITSLICE primitives. One of these internally generated clocks, the divided sample clock, is the clock used to write data into the FIFO (call it FIFO_WR_CLK). A copy of this clock is provided as FIFO_WRCLK_OUT output of the bit slice. Each bit slice has a FIFO_WRCLK_OUT output pin but only bit slices in nibble position zero can route and use this clock.


This is the clock used to pull data out of the FIFO. It needs to have the same frequency as the FIFO_WR_CLK, but there does not need to be a phase relationship between FIFO_RD_CLK and FIFO_WRCLK_OUT clocks. The FIFO read clock can be supplied by a FIFO_WRCLK_OUT of a BITSLICE_0 in the same nibble, byte, or I/O bank, or it can be supplied by a PLL or MMCM generated clock. This clock routes over normal clock nets in the FPGA and requires a clock buffer (BUFG, BUFGCE, or other).


This pin must be High to read the FIFO. When this input pin is left Low, the FIFO output shows new data for every eight FIFO_RD_CLK cycles. This is because the FIFO_RD_EN locks the read pointer of the FIFO while the write pointer advances with each write operation inside the receiver. When the write pointer reaches the eighth pointer position, it loops back to position zero and continues. Because the read pointer is locked, new data appears at the output pins of the bit slice. An empty situation is detected and a FIFO_EMPTY status is generated.


This output is High when the FIFO is empty. When data is written into the FIFO and the write and read point access the same position in the FIFO, an empty situation is detected and signaled by a FIFO_EMPTY pin. The FIFO empty situation is synchronized on the FIFO_RD_CLK and therefore it takes two FIFO_RD_CLK cycles before the FIFO_EMPTY pin changes state. This mechanism makes sure that in normal operation the write pointer always runs ahead of the read pointer.

The behavior described in Table: Behavior of the Clock and Control Inputs of the FIFO is shown in This Figure.

Figure 2-36:      Schematic View of a Receiver FIFO

X-Ref Target - Figure 2-36


The FIFO can be used to align data at the Q pins of different receivers. When the FIFO_WRCLK_OUT is used as FIFO_RD_CLK in an I/O bank, the approach is:

Use the inverted FIFO_EMPTY signal of the used bit slice farthest away from the bit slice receiving the clock and thus generating the FIFO_WRCLK_OUT through an optional flip-flop to all FIFO_RD_EN inputs of used bit slices. The optional flip-flop can be used to help meet timing.

Note:   Farthest means the bit slice at the end of the clock backbone. As shown in This Figure, the clock arrives in the lower nibble of byte_2 and is passed through the inter-byte and inter-nibble backbones to the upper nibble of byte_0.

For high clock rates, timing can be challenging. Solve this by adding pipelining.

When multiple clocks/strobes present, the approach is:

Use a NOR gate combining the FIFO_EMPTY signals of all used bit slices through an optional flip-flop as input for the FIFO_RD_EN of all used bit slices. The optional flip-flop can be used to help meet timing.

The NOR gate waits for the last FIFO_EMPTY to transition Low before triggering the FIFO_RD_EN through the optional flip-flop (see This Figure).


For static timing purposes, a generated clock should be specified as part of the timing constraint when using FIFO_WRCLK_OUT. As an example, assume a DATA_WIDTH = 4 (RX_BITSLICE) and a sample clock of 500 MHz on a port named rx_clk_in. Additionally, assume the instance rx_clock_bitslice_inst (at nibble position zero) with attribute DATA_TYPE = DATA_AND_CLOCK (RX_BITSLICE), and SERIAL_MODE = FALSE (BITSLICE_CONTROL).

The following example XDC generates the required generated clock for the FIFO_WRCLK_OUT pin:

create_clock -name rx_clk -period 2.000 -waveform {0.000 1.000} [get_ports rx_clk_in]

create_generated_clock -divide_by 2 -source [get_ports rx_clk_in] -name fifo_wrclk rx_clock_bitslice_inst/FIFO_WRCLK_OUT

It is good practice to enable application logic in the FPGA after BITSLICE_CONTROL.VTC_RDY goes High. The VTC_RDY signal provides the status that the I/O interface is initialized and up and running.

The FIFO_WRCLK_OUT clock requires the use of a BUFG clock buffer. Although it is possible to connect the FIFO_WRCLK_OUT clock directly to the FIFO_RD_CLK in HDL, because Vivado tools automatically insert a BUFG clock buffer.

To ensure that all RX bit slices start aligned, the rx_clk_in (FIFO_RD_CLK) [(rx_clk_in in the above example)] should be stopped until the RX VTC_RDY signal is asserted.

If you have control of the TX while the RX is coming out of reset, the CLK to the RX side should be stopped until the RX VTC_RDY signal is asserted.

If you do not have control of the TX side, then a bitslip module needs to be implemented in the RX side to ensure all channels are aligned if alignment is needed.

Figure 2-37:      FIFO as Bit Slice Output Synchronizer (Multiple Clocks or Strobes)

X-Ref Target - Figure 2-37


Note 1: When a single clock or strobe is used, use an inverter in the FIFO_EMPTY path of the farthest bit slice to flip-flop instead of a NOR gate. The optional flip-flop helps close timing.

Note 2: When multiple clocks or strobes are used, use a NOR gate assembling the FIFO_EMPTY signals of all used BITSLICES in the path to the flip-flop. The optional flip-flop helps close timing.

As shown in This Figure and This Figure, the latency through the FIFO depends on FIFO_RD_CLK. When the write pointer is updated early with respect to FIFO_RD_CLK, the latency through the FIFO is shorter.

Figure 2-38:      RX_BITSLICE FIFO, DATA_WIDTH = 8

X-Ref Target - Figure 2-38

Figure 2-39:      RX_BITSLICE FIFO, DATA_WIDTH = 4

X-Ref Target - Figure 2-39