HR I/O Banks

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

EQ_LEVEL0

EQ_LEVEL0_DC_BIAS

EQ_LEVEL1

EQ_LEVEL1_DC_BIAS

EQ_LEVEL2

EQ_LEVEL2_DC_BIAS

EQ_LEVEL3

EQ_LEVEL3_DC_BIAS

EQ_LEVEL4

EQ_LEVEL4_DC_BIAS

EQ_NONE (Default)

 

IMPORTANT:   The HR I/O banks with _BIAS equalization values cannot be combined in the same port with the PULLTYPE attribute set to PULLUP, PULLDOWN, or KEEPER.

The EQUALIZATION attribute uses the following syntax in the XDC file:

set_property EQUALIZATION value [get_ports port_name]

Typical AC gain for different values of EQUALIZATION for DDR4 and SGMII interfaces are listed in Table: Typical AC Gain for Different Values of Equalization in DDR4 and SGMII Interfaces.

Table 1-15:      Typical AC Gain for Different Values of Equalization in DDR4 and SGMII Interfaces

Attribute

Value

Estimated Gain (dB)

Equalization in DDR4 interfaces at 2.66 Gb/s

(HP I/O banks)

EQ_LEVEL0

0

EQ_LEVEL1

0.75

EQ_LEVEL2

1.50

EQ_LEVEL3

2.25

EQ_LEVEL4

3.00

Equalization in SGMII interfaces at 1.25 Gb/s

(HR and HP I/O banks)

EQ_LEVEL0/EQ_LEVEL0_DC_BIAS

0

EQ_LEVEL1/EQ_LEVEL1_DC_BIAS

1.50

EQ_LEVEL2/EQ_LEVEL2_DC_BIAS

3.00

EQ_LEVEL3/EQ_LEVEL3_DC_BIAS

4.50

EQ_LEVEL4/EQ_LEVEL4_DC_BIAS

6.00