HSTL Class I (1.2V, 1.5V, or 1.8V)

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

This Figure shows a sample circuit illustrating a termination technique for HSTL class-I for the 1.2V, 1.5V, or 1.8V versions. In a specific circuit, all drivers and receivers must be at the same voltage level (1.2V, 1.5V, or 1.8V); they are not interchangeable (i.e., HSTL_I_12 should only interface with HSTL_I_12). Only HP I/O banks support the DCI standards.

Figure 1-54:      HSTL Class I (1.2V, 1.5V, or 1.8V) Unidirectional Termination

X-Ref Target - Figure 1-54

X16114-hstl-class-i-1_2v-1_5v-or-1_8v-uni-term.jpg

This Figure shows a sample circuit illustrating a termination technique for HSTL class-I for the 1.2V, 1.5V, or 1.8V versions in a bidirectional configuration. In a specific circuit, all drivers and receivers must be at the same voltage level (1.2V, 1.5V, or 1.8V); they are not interchangeable (i.e., HSTL_I_18 should only interface with HSTL_I_18). Only HP I/O banks support the DCI standards.

Figure 1-55:      HSTL Class I (1.2V, 1.5V, or 1.8V) Bidirectional Termination

X-Ref Target - Figure 1-55

X16115-hstl-class-i-1_2v-1_5v-or-1_8v-bidi-term.jpg