HSTL_ I and HSTL_ I

HSTL_ I and HSTL_ I_18

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID

UG571

Release Date

2022-08-31

Revision

1.14 English

Table 1-27: Available I/O Bank Type
HR	HP
Available	Available

HSTL_I and HSTL_ I_18 use V_CCO/2 as a parallel-termination voltage (V_TT).

Optional untuned split input ODT provides Thevenin equivalent resistance of R (where R = Z₀) to the V_CCO/2. The untuned on-die source termination feature (OUTPUT_IMPEDANCE) with optional 40W, 48W, or 60W of driver impedance is available in HP I/O banks. The default value of the driver output impedance is 48W.