IBUF_INTERMDISABLE

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The IBUF_INTERMDISABLE primitive shown in This Figure is available in the HR I/O banks and is similar to the IBUF_IBUFDISABLE primitive in that it has a IBUFDISABLE port that can be used to disable the input buffer during periods that the buffer is not being used. The USE_IBUFDISABLE attribute must be set to TRUE, the IBUFDISABLE port must be controlled, and SIM_DEVICE set to ULTRASCALE for this primitive to have the expected behavior that is specific to the UltraScale architecture. The IBUF_INTERMDISABLE primitive also has an INTERMDISABLE port that can be used to disable the optional on-die receiver termination feature. See Uncalibrated Input Termination in I/O Banks for more details about this feature.

Figure 1-20:      Input Buffer with Input Buffer Disable and On-Die Input Termination Disable (IBUF_INTERMDISABLE)

X-Ref Target - Figure 1-20

X16078-input-buffer-w-input-buffer-disable-and-on-die-input-term-disable-ibuf_intermdisable.jpg

The IBUF_INTERMDISABLE primitive can disable the input buffer and force the O output to the internal logic to a logic-Low when the IBUFDISABLE signal is asserted High. The IBUF_INTERMDISABLE primitive further allows the termination legs to be disabled whenever the INTERMDISABLE signal is asserted High. These features can be combined to reduce power whenever the input is idle. Input buffers that use the VREF power rail (such as SSTL and HSTL) benefit the most from the IBUFDISABLE signal being set to a logic-High because they tend to have higher static power consumption than the non-VREF standards such as LVCMOS and LVTTL.