IDDRE1 Ports

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Note:   IDDRE1 components used in a design are translated and implemented by the Vivado design tools as ISERDESE3 components.

Table: IDDRE1 Ports lists the IDDRE1 ports.

Table 2-1:      IDDRE1 Ports

Port

I/O

Description

Q1, Q2

Output

IDDRE1 register outputs

C

Input

Clock input pin

CB

Input

Inverted clock input pin when IS_C_INVERTED=0 and IS_CB_INVERTED=0

D

Input

Register input from IOB

R

Input

Asynchronous reset, release synchronous to C/CB