IDELAYCTRL

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

If the IDELAYE3 (or ODELAYE3) primitives are instantiated, the IDELAYCTRL module must be instantiated, except when the DELAY_FORMAT is set to COUNT or when mixing component and native mode in native mode designs (see Mixing Native and Non-Native Mode I/O in a Nibble). There is one IDELAYCTRL module per nibble (eight per bank). The IDELAYCTRL module continuously calibrates the individual delay lines configured in TIME mode in its region to their programmed value to reduce the effects of process, voltage, and temperature (PVT) variations. The IDELAYCTRL module calibrates IDELAYE3 (and ODELAYE3) using the system-supplied REFCLK. The frequency value of this REFCLK is applied to individual IDELAYE3 (and ODELAYE3) primitives with an attribute (REFCLK_FREQUENCY). Each delay element in a nibble therefore requires having this attribute set to the same value. This Figure shows a block diagram of the IDELAYCTRL module.

 

TIP:   
1. Resetting the IDELAYCTRL component when the delay lines are used in TIME mode re-invokes the BISC of the nibble that used delay lines.
2. When the EN_VTC pins of the used IDELAYE3 / ODELAYE3 are not set correctly, the IDELAYCTRL.RDY pin never is asserted High by the BISC controller.
3. Within each bank, all of the used IDELAYCTRLs and BITSLICE_CONTROLs have a cascaded RDY signal requiring the reset to be asserted at the same time.

 

CAUTION!   IDELAYE3, ISERDESE3, and IDDRE1 lines used and positioned at I/O positions labeled with DBC and/or QBC are not functional during the BISC stage. These components are available after the IDLEAYCTRL.RDY pin is asserted High.

Figure 2-26:      IDELAYCTRL Module

X-Ref Target - Figure 2-26

X16025-idelayctrl-module.jpg