UltraScale Architecture SelectIO Resources User Guide (UG571)

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1.14 English

Any input signal except clocks can be delayed using the IDELAYE3 primitive and then either forwarded to the device logic directly, or registered in a simple flip-flop, IDDR, or ISERDESE3, using a single data rate (SDR) clock or a double data rate (DDR) clock inside the input/output interconnect (IOI). Clocks should not be delayed using an IDELAYE3, because the IDELAY cannot directly route to the global clock buffers. When clocks must be delayed, use an MMCM or PLL for clock generation, and delay the clocks using the fine-phase shift capabilities.

The IDELAYE3 primitive contains a 512 tap delay line. See the tap resolution in the UltraScale data sheet [Ref 2]. Each individual tap is uncalibrated. However, the logic to calibrate the delay line is available in the IDELAYCTRL component. The IDELAYE3 can be used in two modes, COUNT and TIME.

COUNT mode:

°There is no need to use an IDELAYCTRL component because the delay line is used in the uncalibrated state without voltage and temperature compensation.

°The delay line must be used counting only taps and not counting delay/tap.

-The DELAY_VALUE is expressed as taps (0 to 511).

°Example: Scanning a serial data stream for transitions must be expressed in a number of taps and not translated to time in picoseconds (ps).

TIME mode:

°An IDELAYCTRL component must be used.

°The delay line is calibrated for the requested time value and voltage/temperature compensation ensures this value is kept over time.

°For all delays within a nibble, the REFCLK_FREQUENCY must match the clock frequency for the IDELAYCTRL to ensure the delays are properly aligned. When mixed with native mode, the REFCLK frequency for the BITSLICE_CONTROL should match the REFCLK_FREQUENCY. The DELAY_VALUE is expressed in ps.

The IDELAYE3 primitive is shown in This Figure.

Figure 2-16:      IDELAYE3 Primitive

X-Ref Target - Figure 2-16