UltraScale Architecture SelectIO Resources User Guide (UG571)

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Table: IDELAYE3 Ports lists the IDELAYE3 ports.

Table 2-11:      IDELAYE3 Ports






Cascade delay returning from slave ODELAYE3 DATAOUT. The CASC_RETURN pin is the input cascade delay returning from slave ODELAYE3. The CASC_RETURN of the IDELAYE3 is connected to the slave ODELAYE3 DATAOUT port.



Cascade delay from slave ODELAYE3 CASC_OUT. The CASC_IN pin is used when the IDELAYE3 is used in a cascade chain as a slave input cascade delay from the master ODELAYE3 CASC_OUT.



Cascade delay to ODELAYE3 in cascade. The CASC_OUT pin is used when cascading from an IDELAYE3 to an ODELAYE3. The CASC_OUT port of the IDELAYE3 is connected to the CASC_IN of the ODELAYE3 in cascade.



Clock enable for the delay register clock.

Note:   Delays might take up to three clock cycles (CLK) to be applied. During this time, input data should not change to ensure output data does not glitch.



Clock used to sample LOAD, CE, and INC.

All control inputs to IDELAYE3 primitive (LOAD, CE, and INC) are synchronous to the clock input (CLK). A clock must be connected to this port when IDELAYE3 is configured in VARIABLE or VAR_LOAD. CLK can be locally inverted, and must be supplied by a global or regional clock buffer. The CLK of the IDELAYE3 must be the same CLK as the ISERDESE3 CLKDIV. Unused when configured in FIXED mode.



The increment/decrement is controlled by the enable signal (CE). This interface is only available when the IDELAYE3 is in VARIABLE or VAR_LOAD mode. As long as CE remains High, IDELAYE3 increments or decrements by one tap every CLK cycle. The state of INC determines whether IDELAYE3 increments or decrements: INC = 1 increments, INC = 0 decrements, synchronously to the CLK. If CE is Low, the delay through IDELAYE3 does not change, regardless of the state of INC. When CE transitions High, the increment/decrement operation begins on the next positive clock edge. When CE transitions Low, the increment/decrement operation ceases on the next positive clock edge.

The programmable delay taps in the IDELAYE3 primitive wraps around to the start or end of the taps. When the last tap delay is reached (tap 512), a subsequent increment function returns to tap 0. The same applies to the decrement function—a decrement from zero moves to tap 512.



Load counter value from the attribute DELAY_VALUE or the CNTVALUEIN bus when High.

When in VAR_LOAD mode and UPDATE_MODE=ASYNC, the IDELAYE3 load port, LOAD, loads the value set by the CNTVALUEIN into registers connected to the delay line tap selection logic. The value present at CNTVALUEIN[8:0] is the new tap value. The LOAD signal is an active-High signal and is synchronous to the input CLK signal. Wait at least one clock cycle after applying a new value on the CNTVALUEIN bus before applying the LOAD signal. CE must be held Low during LOAD operation.

When in UPDATE_MODE = SYNC mode, connect LOAD to ground (GND).

Note:   Delays may take up to three clock cycles (CLK) to be applied. During this time, input data should not change to ensure output data does not glitch.



The CNTVALUEIN pins are used for dynamically switching the loadable tap value. The CNTVALUEIN is the number of taps required. The new value is best applied one clock cycle before applying the LOAD signal. The delay line can be changed from 1 to 8 taps at a time.



The CNTVALUEOUT pins are used for reporting the current tap value and reads out the amount of taps in the current delay. When EN_VTC is High, CNTVALUEOUT is updated by the IDELAYCTRL.



The DATAIN input is directly driven by the interconnect logic providing a logic accessible delay line. The data is driven back into the interconnect logic through the DATAOUT port with a delay set by the DELAY_VALUE. DATAIN can be locally inverted. The data cannot be driven to an IOB.



The IDATAIN input is driven by its associated IOB.



Delayed data from the two data input ports. DATAOUT drives ILOGIC (IFD/IDDR), ISERDESE3, and logic in the FPGA.



The RST pin (reset) is an asynchronous input. When the IDELAYE3 is reset, the delay is set to the value defined by the DELAY_VALUE attribute. RST must follow the Component Mode Reset Sequence when used with the IDELAYCTRL. After IDELAYCTRL.RDY goes High, IDELAY can be used for normal operation.



EN_VTC: Enable voltage temperature compensation.

High: Enables IDELAYCTRL to keep delay constant over VT.

Low: VT compensation is disabled.

To make delay line updates, EN_VTC must be kept Low. EN_VTC is an asynchronous input but must follow the Component Mode Reset Sequence when used with the IDELAYCTRL.