ISERDESE3

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The ISERDESE3 element is available to perform input deserialization for designs migrating from previous FPGA families or for designs not requiring native mode primitives. The ISERDESE3 in UltraScale devices is a serial-to-parallel converter with specific clocking and logic features designed to facilitate the implementation of high-speed source-synchronous applications. The ISERDESE3 avoids the additional timing complexities encountered when designing deserializers in the device logic.

There are some differences between the ISERDESE3 and its predecessors. ISERDESE3 does not have:

BITSLIP input performing a bitslip operation synchronous to CLKDIV.

Selectable CE inputs able to function as a 2:1 serial-to-parallel converter clocked by CLKDIV.

OFB input, being a direct connection between the OSERDES serial output and this input.

SHIFTIN and SHIFTOUT pins allow extending the deserialization capability up to 14 bits by cascading two ISERDES using direct connections.

The ISERDESE3 can deserialize an incoming signal by 2 or 4 in SDR data capture, and by 4 or 8 in DDR data capture mode. When used for SDR data capture, the valid outputs are every other data output pin. For example, when used as a 1:4 deserializer using an SDR clock, the data width should be set to 8, and the data received is taken from Q0, Q2, Q4, and Q6. Details of which SerDes output pins to use and which value to apply to the DATA_WIDTH attribute are shown in Table: ISERDESE3 Output Connections in SDR and DDR Modes .

 

TIP:   The first serial bit received in a word is Q0.

Table 2-5:      ISERDESE3 Output Connections in SDR and DDR Modes 

SDR or DDR

Required Ratio

DATA_WIDTH Attribute to Apply to ISERDESE3

SerDes Output Data Bits to Use

DDR

1:8

8

Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0

DDR

1:4

4

Q3, Q2, Q1, Q0

SDR

1:8

N/A

N/A

SDR

1:4

8

Q6, Q4, Q2, Q0

SDR

1:2

4

Q2, Q0

Other deserialization ratios and word alignment schemes are possible through the use of additional logic resources in the FPGA logic (see Bitslip in Logic Application Note (XAPP1208) [Ref 10]. The ISERDESE3 also contains a shallow eight entry FIFO that can optionally be used for clock domain transfers. When not used, the FIFO control signals should be connected to GND. When using the FIFO, the FIFO_RD_EN should be driven by the inverted FIFO_EMPTY signal to ensure the FIFO_write and read pointers do not overlap every eight clock cycles. As shown in This Figure and This Figure, latency through the FIFO depends on FIFO_RD_CLK. When the write pointer is updated early with respect to FIFO_RD_CLK the latency through the FIFO is shorter.

Because clock routing can vary, the MMCM with the ZHOLD compensation compensates for the clock routing. To ensure all of the clock outputs from the MMCM are properly compensated for, the CLOCK_DELAY_GROUP must be used (see This Figure). To ensure the ISERDES is properly aligned after a reset, see Component Mode Reset Sequence.

When the clocks are not compensated for, such as when clock-capable inputs are directly connected to clock buffers (BUFG, BUFGCE, BUFGCE_DIV), additional bitslip logic is required. See Bitslip in Logic Application Note (XAPP1208) [Ref 10].

Figure 2-12:      ISERDES FIFO Latency with DATA_WIDTH = 8

X-Ref Target - Figure 2-12

X19091-ldjQJEXa.jpg
Figure 2-13:      ISERDES FIFO Latency with DATA_WIDTH = 4

X-Ref Target - Figure 2-13

X19090-CTOLQPqX.jpg