ISERDESE3 Ports

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Table: ISERDESE3 Ports lists the ISERDESE3 ports.

Table 2-6:      ISERDESE3 Ports

Port

I/O

Type

Description

CLK

Input

Clock

High-speed clock input. Clock serial input data stream.

CLK_B

Input

Clock

Inverted version of CLK when IS_CLK_INVERTED=0 and IS_CLK_B_INVERTED=0.

CLKDIV

Input

Clock

Low-speed divided clock input.

D

Input

Data

Serial input data Synchronous to CLK/CLK_B.

Q[7:0]

Output

Data

Registered outputs. Synchronous to FIFO_RD_CLK when FIFO_ENABLE is TRUE.

RST

Input

Reset

Asynchronous reset.

FIFO_RD_CLK

Input

Clock

FIFO read clock.

FIFO_RD_EN

Input

Enable

Enables reading the FIFO when asserted.

FIFO_EMPTY

Output

 

Indicates the FIFO is empty when asserted.

INTERNAL_DIVCLK

Output

Clock

Reserved