The input and output delays are each 512 taps deep (the delay of one tap is provided in the UltraScale device data sheets as TODELAY_RESOLUTION [Ref 2]. The delay element can be controlled either from the BITSLICE_CONTROL via the RIU interface or directly from interconnect logic using the delay control signals on the RXTX_BITSLICE (CLK, CE, INC, LOAD, CNTVALUEIN[8:0], CNTVALUEOU[8:0], RST_DLY, and EN_VTC).
The delay lines can be used in two distinct modes, TIME and COUNT. In TIME mode, the initial delay (DELAY_VALUE) is defined in ps; in COUNT mode the initial delay is provided as a number of taps. When TIME mode is used, the built-in self-calibration (BISC) controller calibrates and maintains the delay line.