Inter-byte Clocking Precautions

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

For the following or similar conditions, the arriving clock in the lower nibble must be passed via inter-byte clock routes to the lower nibble of a upper or lower byte and then routed in the byte to the upper nibble by inter-nibble clocking paths as shown in This Figure:

It is assumed that the BISC controller in the BITSLICE_CONTROL primitive is turned on by SELF_CALIBRATE = ENABLE.

The received clock arrives at the lower nibble BITSLICE_0 of byte_2 of the I/O bank.

The bit slices used to capture data are placed in the upper nibble of byte_0 in the I/O bank.

In these cases, observe this condition:

For a design using inter-byte clocking and SELF_CALIBRATE is enabled, a BITSLICE_0 must be instantiated in the nibble receiving the inter-byte clock.

The BITSLICE_0 that needs to be instantiated in the above-mentioned case must be configured with the attribute DATA_TYPE set to DATA.

The instantiated BITSLICE_0 can be used for data capture.

When the instantiated BITSLICE_0 is not used at all, you must connect an input buffer to the bit slice for correct software behavior.

 

CAUTION!   All bit slices in a nibble with an instantiated BITSLICE_0 used to pass a clock input from CLK_FROM_EXT use the clock of the CLK_FROM_EXT input as a data capture clock. The same applies when the CLK_FROM_EXT is routed by inter-nibble clocking to an upper or lower nibble. For the upper nibble, BITSLICE_0 is the equivalent of BITSLICE_6 for a byte group. See This Figure for an explanation of bitslice numbering within a byte and nibble.

Figure 2-71:      Inter-byte Clocking with BITSLICE_0 Bypass

X-Ref Target - Figure 2-71

X16956-interbyte-clocking-with-bitslice_0-bypass.jpg

Example 1:

The clock arrives in the lower nibble of byte_2 and data inputs are placed in the upper nibble of byte_0. No other bit slices in the I/O bank are used.

The clock must pass from CLK_TO_EXT_SOUTH of the lower nibble in byte_2 as a pass-through in the lower nibble of byte_1 and then route to the CLK_FROM_EXT in the lower nibble of byte_0.

Because no bit slices are used in the lower nibble of byte_1, a RXTX_BITSLICE or RX_BITSLICE and BITSLICE_CONTROL must be instantiated in bit slice position zero of the nibble. The bit slice positioned in bit slice zero must be configured with DATA_TYPE = DATA.

The instantiated bit slice and BITSLICE_CONTROL do not need any connection except for the PLL_CLK, RIU_CLK, and input delay line CLK.

It might be necessary to LOC the bit slice and BITSLICE_CONTROL in the FPGA I/O architecture.

The inter-nibble clock must be used to route the clock from the lower nibble into the upper nibble of byte_0.

Example 2:

This same situation is similar to example 1, but the clock arrives in the upper nibble of byte_2.

The clock must pass from CLK_TO_EXT_SOUTH of the upper nibble in byte_2 as a pass-through in the upper nibble of byte_1 and then route to the CLK_FROM_EXT in the upper nibble of byte_0.

Because no bit slices are used in the upper nibble of byte_1, a RXTX_BITSLICE or RX_BITSLICE and BITSLICE_CONTROL must be instantiated in bit slice position zero of the nibble.

The instantiated bit slice and BITSLICE_CONTROL do not need any connection except for the PLL_CLK, RIU_CLK, and input delay line CLK.

It might be necessary to LOC the bit slice and BITSLICE_CONTROL in the FPGA I/O architecture.

No inter-nibble clock is needed because the inter-byte clock arrives at the upper nibble of byte_0.

Example 3:

This same situation is similar to example 1, but all bit slices in all nibbles of bytes_2, _1, and _0 are used except BITSLICE_0 in the lower nibble of byte_1.

The inter-nibble clock must be used to route the clock from the lower nibble into the upper nibble of byte_2.

The inter-byte clock must be used to route the clock from the CLK_TO_EXT_SOUTH of the lower nibble in byte_2 to the CLK_FROM_EXT of the lower nibble of byte_1.

Because BITSLICE_0 of that nibble is not used, one must be instantiated.

A BITSLICE_CONTROL does not need to be instantiated because one is used for the other bit slices in the nibble.

The inter-nibble clock must be used to route the clock from the lower to the upper nibble of byte_1.

The instantiated BITSLICE_0 does not need a LOC attribute because the BITSLICE_CONTROL is already used for the other bit slices in the nibble.

The inter-byte clock must be used to route the clock from the CLK_TO_EXT_SOUTH of the lower nibble in byte_1 to the CLK_FROM_EXT of the lower nibble of byte_0.

The inter-nibble clock must be used to route the clock from the lower to the upper nibble of byte_0.