Internal VREF

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

The VREF supply required by the SSTL, HSTL, HSUL, and POD standards is generated inside the device, removing the need to provide a VREF supply rail on the PCB or allocate a package pin for VREF. The internally generated VREF is sourced from the VCCO supply rail.

The constraint INTERNAL_VREF is assigned on a bank-wide basis. The INTERNAL_VREF attribute uses the following syntax in the XDC file:

set_property INTERNAL_VREF voltage [get_iobanks bank_number]

Example 1: INTERNAL_VREF for Bank 84 using HSTL_II (1.5V), which requires a 0.75V reference voltage, uses the following constraint:

set_property INTERNAL_VREF 0.75 [get_iobanks 84]

Example 2: INTERNAL_VREF for Bank 65 using HSTL_II_18 (1.8V), which requires a 0.9V reference voltage, uses the following constraint:

set_property INTERNAL_VREF 0.90 [get_iobanks 65]

The rules for using INTERNAL_VREF in an HD bank are:

One value of VREF can be set for the bank.

INTERNAL_VREF can only be set to the nominal reference voltage value of a given I/O standard.

Valid settings of INTERNAL_VREF are listed, but must be selected to half of the Vcco level. Valid levels in HD I/O banks are 0.60V, 0.675V, 0.75V, and 0.9V.