UltraScale Architecture SelectIO Resources User Guide (UG571)

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As device footprints increase and system clock speeds get faster, PC board design and manufacturing becomes more difficult. With ever faster edge rates, maintaining signal integrity becomes a critical issue. PC board traces must be properly terminated to avoid reflections or ringing.

To terminate a trace, resistors are traditionally added to make the output and/or input match the impedance of the receiver or driver to the impedance of the trace. However, due to increased device I/Os, adding resistors close to the device pins increases the board area and component count, and can in some cases be physically impossible. To address these issues and to achieve better signal integrity, Xilinx developed the digitally controlled impedance (DCI) technology.

Depending on the I/O standard, DCI can either control the output impedance of a driver, or add a parallel termination present at the receiver, with the goal of accurately matching the characteristic impedance of the transmission line. DCI actively adjusts these impedances inside the I/O to calibrate to an external precision reference resistor placed on the VRP pin. This compensates for changes in I/O impedance due to process variation. It also continuously adjusts the impedances to compensate for variations of temperature and supply voltage fluctuations. Many designs require the use of multiple DCI reference VRP pins. In these scenarios, a unique reference resistor is required for each VRP pin.


IMPORTANT:   For all DCI I/O standards, the external reference resistor (RVRP) should be 240W.

For the I/O standards with controlled parallel termination, DCI provides the parallel termination for receivers. This eliminates the need for termination resistors on the board, reduces board routing difficulties and component count, and improves signal integrity by eliminating stub reflection. Stub reflection occurs when termination resistors are located too far from the end of the transmission line. With DCI, the termination resistors are as close as possible to the output driver or the input buffer, thus, eliminating stub reflections. The exact value of the termination resistors is determined by the ODT attribute for controlled parallel termination. The exact driver termination value is determined by the OUTPUT_IMPEDANCE attribute for the controlled impedance driver. DCI is only available in HP I/O banks. DCI is not available in HR I/O banks.

DCI uses one multipurpose reference VRP pin in each I/O bank to control the impedance of the driver or the parallel-termination value for all of the I/Os of that bank.


IMPORTANT:   When using DCI standards, the VRP pin must be terminated to GND by a reference resistor. The value of the resistor should be 240W.

To implement DCI in a design:

1.Assign one of the DCI I/O standards in an HP I/O bank (see Table: All DCI I/O Standards Supporting Split-Termination DCI ).

2.Connect the VRP multi-function pin to a precision resistor (240W) tied to GND.

3.Set the desired termination value using the ODT attribute for all applicable I/Os with controlled parallel terminations. Set the termination value using the OUTPUT_IMPEDANCE attribute for all applicable I/Os with a controlled impedance driver.

If several I/O banks in the same I/O bank column are using DCI, the internal VRP node can be cascaded so that only one VRP pin for all of the I/O banks in the entire I/O column is required to be connected to a precision resistor. This option is called DCI cascading as is detailed in DCI Cascading. This section also describes how to determine if I/O banks share the same I/O bank column. If DCI I/O standards are not used in the bank, the VRP pin is available as a standard I/O pin. The UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) [Ref 3] gives detailed pin descriptions.

DCI adjusts the impedance of the I/O by selectively turning resistors in the I/Os on or off. The adjustment starts during the device start-up sequence. By default, the DONE pin does not transition High until the first part of the impedance adjustment process is completed.

The DCI calibration can be reset by instantiating the DCIRESET primitive. Toggling the RST input to the DCIRESET primitive while the device is operating resets the DCI state machine and restarts the calibration process. All I/Os using DCI are unavailable until the LOCKED output from the DCIRESET block is asserted. This functionality is useful in applications where the temperature and/or supply voltage changes significantly from device power-up to the nominal operating condition.

For controlled impedance output drivers, the exact value of the driver terminations is determined by the OUTPUT_IMPEDANCE attribute. For the I/O standards that support parallel termination, DCI creates a Thevenin equivalent, or split-termination resistance to the VCCO/2 voltage level, or a single-termination resistance to the VCCO voltage level. The value of split-termination resistors are determined by the ODT attribute. For POD and HSUL standards, DCI supports single termination to VCCO. The value of the termination resistance is determined by the ODT attribute.