Introduction to High Density I/O Banks

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

High-density (HD) I/O banks are SelectIO resources designed to support a wide range of I/O standards with voltages ranging from 1.2V to 3.3V. HD I/Os are optimized for single-ended, voltage-referenced, and pseudo-differential I/O standards operating at data rates of up to 250 Mb/s. Limited support for true differential inputs (with external termination) is also available to support LVDS and LVPECL clock inputs. HD I/Os also contain interface logic including registers and static delay lines to support asynchronous, system synchronous, and clock-based source synchronous interfaces. Table: Supported Features in the HD I/O Banks highlights the features supported in HD I/O banks.

 

IMPORTANT:   HD I/O banks are only supported in Zynq® UltraScale+™ devices, Kintex® UltraScale+ devices, and some Virtex® UltraScale+ devices.

Table 3-1:      Supported Features in the HD I/O Banks

Features

HD I/O Bank Support

3.3V I/O standards

LVTTL and LVCMOS

2.5V I/O standards

LVCMOS and LVDS/SUB_LVDS(1)

1.8V I/O standards

LVCMOS, SSTL(2)(3), and HSTL(2)(3)

1.5V I/O standards

LVCMOS, SSTL(2)(3), and HSTL(2)(3)

1.35V I/O standards

SSTL(2)(3)

1.2V I/O standards

LVCMOS, SSTL(2)(3), and HSTL(2)(3)

LVDS and LVPECL

Inputs supported (with external termination).(1)

VREF

Internal VREF supported in HD I/O banks (no external VREF).

Maximum data rate

250 Mb/s DDR

Output drive strength control

Supported

Output slew rate control

Supported

Pull-up, pull-down, and keeper

Supported

ILOGIC for SDR and DDR interfaces

Supported

OLOGIC for SDR and DDR interfaces

Supported

ZHOLD (static delay for zero hold)

Supported

Internal differential termination (DIFF_TERM)

Not supported

Digitally controlled impedance (DCI) and DCI cascading

Not supported

ISERDES, OSERDES

Not supported

Programmable delay (IDELAY, ODELAY)

Not supported

DQS_BIAS

Not supported

Notes:

1.Does not support differential termination or LVDS/SUB_LVDS outputs. These features are supported in high-performance I/O (HP I/O) banks available in the same device.

2.Optional 50W on-die input termination is supported for SSTL and HSTL inputs.

3.SSTL, HSTL, and HSUL support enables legacy and chip-to-chip interfaces. There is no support for interfaces to DRAM memory devices (DDR3, DDR4, LPDDR2, or LPDDR3).