LVDS and LVDS_25

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Low-voltage differential signaling (LVDS) is a powerful high-speed interface in many system applications. The I/Os are designed to be compatible with the EIA/TIA electrical specifications for LVDS system and board design. With the use of an LVDS current-mode driver in the IOBs and the optional internal differential termination feature, the need for external source termination in point-to-point applications is eliminated. UltraScale devices provide a flexible solution for creating an LVDS design.

The LVDS I/O standard is only available in the HP I/O banks. It requires a VCCO to be powered at 1.8V for outputs and for inputs when the optional internal differential termination is implemented.

DIFF_TERM_ADV = TERM_100

DIFF_TERM = TRUE

The LVDS_25 I/O standard is available in the HR I/O banks. It requires a VCCO to be powered at 2.5V for outputs and for inputs when the optional internal differential termination is implemented.

DIFF_TERM_ADV = TERM_100

DIFF_TERM = TRUE

Table 1-54:      Available I/O Bank Type 

HR

HP

Available for LVDS_25 only

Available for LVDS only