LVTTL

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English
Table 1-16:      Available I/O Bank Type 

HR

HP

Available

N/A

Low voltage TTL (LVTTL) is a general-purpose EIA/JESD standard for 3.3V applications that uses a single-ended CMOS input buffer and a push-pull output buffer. This standard requires a 3.3V output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a termination voltage (VTT). This standard is defined by JEDEC (JESD 8C.01) [Ref 7].

Sample circuits illustrating both unidirectional and bidirectional LVTTL termination techniques are shown in This Figure and This Figure. These two diagrams show examples of source-series and parallel terminated topologies.

This Figure shows unidirectional terminated topologies.

Figure 1-47:      LVTTL Unidirectional Termination

X-Ref Target - Figure 1-47

X16107-lvttl-uni-term.jpg

This Figure shows a bidirectional, parallel-terminated topology.

Figure 1-48:      LVTTL Bidirectional Termination

X-Ref Target - Figure 1-48

X16108-lvttl-bidi-term.jpg

Table: Allowed Attributes for the LVTTL I/O Standards  details the allowed attributes that can be applied to the LVTTL I/O standard. This standard is only available in the HR I/O banks. Support is implied for primitives that are derivatives of the primitives listed in Table: Allowed Attributes for the LVTTL I/O Standards  (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to the SelectIO Interface Primitives section for all supported derivatives.

Table 1-17:      Allowed Attributes for the LVTTL I/O Standards 

Attributes

Primitives

IBUF

OBUF/OBUFT/IOBUF

Allowed Values

Default

IOSTANDARD

LVTTL

LVTTL

DRIVE

N/A

4, 8, 12, or 16

12

SLEW

N/A

FAST or SLOW

SLOW