As described in RXTX_BITSLICE , a BITSLICE_CONTROL is connected to one or more bit slices (RX_BITSLICE/TX_BITSLICE or RXTX_BITSLICE) in a nibble, with the position of the bit slice I/O determined by the dedicated control bus connections.
If there are unused I/O bit slices in a native mode nibble, other I/O can be positioned (mixed) in the free locations. No special connectivity is necessary in the design because the I/O buffers are connected in the usual manner. All SelectIO component primitives (IFD/OFD, IDDR/ODDR, IDELAY/ODELAY, ISERDESE3/OSERDESE3) can also be used when mixing in a native mode nibble.
For designs with multiple nibbles being used within a bank, care must be taken when resetting the IDELAYCTRLs and BITSLICE_CONTROLs. The reset for all used BITSLICE_CONTROLs and IDELAYCTRLs within a bank must be released at the same time due to the DLY_RDY connections between the BITSLICE_CONTROLs within a bank. For example, if a bank has two different interfaces, both interfaces should be controlled by a single reset to ensure that calibration completes. Failure to do so might result in DLY_RDY for one of the interfaces not asserting. To place IDELAYs/ODELAYs (component) into a nibble that already contains TX_BITSLICE (native), use the IODELAY_GROUP constraint and placement constraints for the delay elements. An IDELAYCTRL element must not be associated with the mixed Component mode IDELAYE3/ODELAYE3 instances because the native mode BITSLICE_CONTROL is already configured to carry out the delay calibration in the nibble. To implement mixed delays using the Vivado Design Suite, place the IODELAY_GROUP constraint on both the BITSLICE_CONTROL instance as well as on each primitive IDELAYE3/ODELAYE3 instance to be mixed in that nibble. The syntax is as follows:
set_property IODELAY_GROUP MIXED_DELAY_GROUP_NAME [get_cells BITSLICE_CONTROL_INST]
set_property IODELAY_GROUP MIXED_DELAY_GROUP_NAME [get_cells COMPONENT_MODE_DELAY_INST]
Each nibble requires an IODELAY_GROUP, which corresponds to a BITSLICE_CONTROL or IDELAYCTRL within that nibble. Because each nibble only contains a single IDELAYCTRL or BITSLICE_CONTROL, each nibble can only contain IDELAYs/ODELAYs from a single IODELAY_GROUP.
The frequency of REFCLK connected to BITSLICE_CONTROL should be specified as the REFCLK_FREQUENCY attribute of the IDELAYE3/ODELAYE3 primitive instances. All of the IDELAYE3/ODELAYE3 primitives within the nibble must match the frequency for REFCLK to ensure the delays set by the DELAY_VALUE are calibrated correctly. The VTC_RDY signal from the BITSLICE_CONTROL indicates that calibration is completed for all native and non-native delays in the mixed nibble.
When not mixing native and Component mode delays, it is not necessary to specify the IODELAY_GROUP constraint for BITSLICE_CONTROLs.
An example mixed-mode byte is illustrated in This Figure .
Example XDC constraints for mixed nibbles depicted in This Figure are listed:
set_property IODELAY_GROUP UPPER_GROUP [get_cells UPPER_BITSLICE_CONTROL_INST]
set_property IODELAY_GROUP UPPER_GROUP [get_cells UPPER_RXBIT_0/IDELAYE3]
set_property IODELAY_GROUP LOWER_GROUP [get_cells LOWER_BITSLICE_CONTROL_INST]
set_property IODELAY_GROUP LOWER_GROUP [get_cells LOWER_RXBIT_0/IDELAYE3]
set_property IODELAY_GROUP LOWER_GROUP [get_cells LOWER_TXBIT_0/ODELAYE3]
set_property PACKAGE_PIN PAD12 [get_ports UPPER_RXBIT_0]
set_property PACKAGE_PIN PAD11 [get_ports UPPER_TXOUT_0_N]
set_property PACKAGE_PIN PAD10 [get_ports UPPER_TXOUT_0_P]
…
set_property PACKAGE_PIN PAD3 [get_ports LED_OUT]
set_property PACKAGE_PIN PAD2 [get_ports LOWER_RX_BIT_0]
set_property PACKAGE_PIN PAD1 [get_ports LOWER_TX_BIT_0]
Notes on the example in This Figure :
• Upper nibble
° There is one incoming differential strobe/clock located at the lower bit slice position 0, using pads 6 and 7. This is captured using a native primitive RX_BITSLICE (DATA_AND_CLOCK).
° There are two further native mode primitive DATA bit slices, at bit slice positions 2 (RX_BITSLICE) and 4 (TX_BITSLICE), each using differential I/O.
° There is one mixed Component primitive IDELAYE3 driving straight to the internal logic in the upper bit slice position 6, at pad 12 using a single-ended IBUF.
° The XDC constraint defines IODELAY_GROUP called UPPER_GROUP to group the Component primitive IDELAYE3 with the upper BITSLICE_CONTROL instance.
° All 7 of the I/O pads are used in the upper nibble.
• Lower nibble
° Two native primitive TX_BITSLICES are located in the upper two bit slice positions 4 and 5, driving single-ended OBUFs at pads 4 and 5.
° Two mixed Component primitive delays are located in the lower nibble, one IDELAYE3 driving an ISERDESE3 at position 1 and one OSERDESE3 driving an ODELAYE3 at position 0.
° There is one other non-native I/O located in the lower nibble. Signal LED_OUT directly drives an I/O without any I/O logic elements used. This is achieved by LOCing the I/O into the correct package pin.
° The XDC constraint defines the IODELAY_GROUP called the LOWER_GROUP to group the Component primitive ODELAYE3 and IDELAYE3 with the lower BITSLICE_CONTROL instance.
° Five of the six I/O pads in the lower nibble are used. Another I/O could potentially be placed in the unused pad 2 by applying the appropriate PACKAGE_PIN property as was done in the XDC example for LED_OUT, assuming the proposed I/O meets the SelectIO bank combination rules.
° A PLL is used to supply the master clock for both upper and lower BITSLICE_CONTROLs using the PLL_CLK dedicated path. Because this clock is used as the BISC reference clock for the mixed Component mode, IDELAYE3/ODELAYE3 primitives (as well as any native mode delays), the frequency of this clock should be set for each Component primitive delay instance, on the REFCLK_FREQUENCY attribute. No Component primitive IDELAYCTRL elements should be associated with the Component primitive delay instances in this byte.
° The VTC_RDY signal from the two BITSLICE_CONTROL signals signifies that BISC is complete for the two nibbles, the same function that the Component primitive IDELAYCTRL RDY signal does for non-mixed Component primitive nibbles.