Native Mode Bring-up and Reset

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

To bring up a design in an UltraScale device using native SelectIO primitives, a specific set of steps must be followed to apply or release the reset. Follow the described steps to ensure all clocks are phase-aligned and related as shown in This Figure between PLL/MMCM, BITSLICE_CONTROL, and bit slices.

Figure 2-61:      PLL and Reset Bring-up Sequence

X-Ref Target - Figure 2-61

X19013-pll-reset-bringup.jpg

In This Figure, PLL.CLKOUTPHY_EN disables the BITSLICE_CONTROL.PLL_CLK until after reset has been removed. For detailed descriptions for the clocking requirements, see Clocking in Native Mode.

PLL_CLK/REFCLK entering BITSLICE_CONTROL should be disabled until all the BITSLICE_CONTROLs and RXTX_BITSLICEs are reset and their resets have been safely removed. This ensures a deterministic bring-up of the interface.

At startup of a design or after a reset has been applied to the application in the FPGA, the reset must be released using the following sequence: