To bring up a design in an UltraScale device using native SelectIO primitives, a specific set of steps must be followed to apply or release the reset. Follow the described steps to ensure all clocks are phase-aligned and related as shown in This Figure between PLL/MMCM, BITSLICE_CONTROL, and bit slices.
PLL_CLK/REFCLK entering BITSLICE_CONTROL should be disabled until all the BITSLICE_CONTROLs and RXTX_BITSLICEs are reset and their resets have been safely removed. This ensures a deterministic bring-up of the interface.
At startup of a design or after a reset has been applied to the application in the FPGA, the reset must be released using the following sequence: