TIP: To achieve required timing constraints for a design set up as in This Figure, it might be necessary to LOC the flip-flop in FPGA logic close to the ODDRE1/OSERDESE3 used.
In the single 3-state solution, the flip-flop driving the 3-state is placed in the internal logic with the ODDRE1 placed in a bit slice site. To have the 3-state flip-flop also placed in the same bit slice site as the ODDRE1, the arrangement shown in This Figure can be altered to tie the 3-state D1 and D2 inputs together to a common 3-state.
This Figure shows the serialized ODDRE1 circuit. The SR and C pins of both ODDRE1s must have a common source to allow the implementation software to transform this circuit into a single OSERDESE3 instance that supports the desired function. Although the previously discussed circuit (using ODDRE1 primitives) is preferred, a different way to achieve the discussed circuit is provided in OSERDESE3.