ODDRE1

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

UltraScale devices have registers in the bit slice to implement output DDR registers as in previous FPGA generations. This feature is accessed when instantiating the ODDRE1 primitive. DDR multiplexing is automatic when using the ODDRE1. No manual control of the multiplexer select is needed. This control is generated from the clock.

The ODDRE1 primitive supports only the SAME_EDGE mode of operation. The SAME_EDGE mode allows designers to present both data inputs to the ODDRE1 primitive on the rising edge of the ODDRE1 clock, saving CLB and clock resources and increasing performance. This mode is also supported for 3-state control. The timing diagram of the output DDR is shown in This Figure.

Figure 2-8:      Output DDR Timing

X-Ref Target - Figure 2-8

X16009-output-ddr-timing.jpg

This Figure shows a block diagram of the ODDRE1 primitive.

Figure 2-9:      ODDRE1 Primitive Block Diagram

X-Ref Target - Figure 2-9

X16010-oddre1-primitive-block-diag.jpg

Note:   ODDRE1 components used in a design are translated and implemented by the Vivado design tools as OSERDESE3 components.