Table: ODDRE1 Ports
lists the ODDRE1 ports.
Table 2-3:
ODDRE1 Ports
|
Port
|
I/O
|
Description
|
|
Q
|
Output
|
ODDRE1 register output
|
|
C
|
Input
|
Clock input pin
|
|
D1, D2
|
Input
|
ODDRE1 register inputs
|
|
SR
|
Input
|
Asynchronous set/reset. Release synchronously. When SR is asserted, the Q output is asynchronously set to the SRVAL. The SRVAL is held for 4 clock cycles before resuming normal operation.
|