ODELAYE3

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID
UG571
Release Date
2022-08-31
Revision
1.14 English

Any output signal can be delayed using the ODELAYE3 primitive, having been either forwarded from the device logic directly or registered in a simple flip-flop or OSERDES using an SDR or DDR clock.

The ODELAYE3 primitive (This Figure) contains a 512-tap delay line. (See the tap resolution in the UltraScale device data sheet [Ref 2]). Each individual tap is uncalibrated. However, the logic to calibrate the delay line is available in the IDELAYCTRL component.

The ODELAYE3 can be used in two modes:

COUNT mode:

°No need to use an IDELAYCTRL component because the delay line is used in the uncalibrated state without voltage and temperature compensation.

°The delay line must count only taps and not count delay/tap.

°The DELAY_VALUE is expressed as taps (0 to 511).

°Example: Scanning a serial data stream for transitions must be expressed in a number of taps and not translated to time in ps.

TIME mode:

°An IDELAYCTRL component must be used.

°The delay line is calibrated for the requested time value and voltage/temperature compensation makes sure that this value is kept over time.

°The DELAY_VALUE is expressed in ps.

Figure 2-23:      ODELAYE3 Primitive

X-Ref Target - Figure 2-23

X16023-odelaye3-primitive.jpg